Epson S1D13504 manual Clock Configuration Register, Pixel Panning Register

Epson Research and Development							Page 101
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				b
Pixel Panning Register
REG[18h]							RW
Screen 2	Screen 2	Screen 2	Screen 2	Screen 1	Screen 1	Screen 1	Screen 1
Pixel Panning	Pixel Panning	Pixel Panning	Pixel Panning	Pixel Panning	Pixel Panning	Pixel Panning	Pixel Panning
Bit 3	Bit 2	Bit 1	Bit 0	Bit 3	Bit 2	Bit 1	Bit 0

This register is used to control the horizontal pixel panning of screen 1 and screen 2. Each screen can be independently panned to the left by programming its respective Pixel Panning Bits to a non- zero value. This value represents the number of pixels panned. The maximum pan value is dependent on the display mode as shown in the table below.

	Table 8-8: Pixel Panning Selection
	Number of Bits-Per-Pixel	Screen 2 Pixel Panning Bits Used
	1	Bits [3:0]
	2	Bits [2:0]
	4	Bits [1:0]
	8	Bit 0
	15/16	---
	Smooth horizontal panning can be achieved by a combination of this register and the Display Start
	Address register. See Section 10, “Display Configuration” on page 116 and S1D13504
	Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for details.
bits 7-4	Screen 2 Pixel Panning Bits [3:0]
	Pixel panning bits for screen 2.
bits 3-0	Screen 1 Pixel Panning Bits [3:0]
	Pixel panning bits for screen 1.

8.2.5

Clock Configuration Register

Clock Configuration Register

REG[19h]

RW

n/a

n/a

n/a

n/a

n/a

MCLK Divide

PCLK Divide

PCLK Divide

Select

Select Bit 1

Select Bit 0

bit 2

MCLK Divide Select

When this bit = 1 the memory clock (MCLK) frequency is half of the input clock frequency. When

this bit = 0 the memory clock frequency is equal to the input clock frequency.

bits 1-0

PCLK Divide Select Bits [1:0]

These bits determine the amount of divide from the memory clock to generate the pixel clock (PCLK):

Table 8-9: PCLK Divide Selection

PCLK Divide Select Bits [1:0]

MCLK/PCLK Frequency Ratio

00

1

01

2

10

3

11

4

See Section 11.2, “Frame Rate Calculation” on page 120 for selection of PCLK frequency.

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18