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Epson Research and Development

 

Vancouver Design Center

 

 

3.2 Generic MPU Host Bus Interface Signals

The interface requires the following signals:

BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13504. It is separate from the pixel clock (CLKI) and is typically driven by the host CPU system clock.

The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the CPU address and data bus, respectively. The hardware engineer must ensure that MD4 selects the proper endian mode upon reset.

Chip Select (CS#) is driven by decoding the high-order address lines to select the proper IO or memory address space.

M/R# is driven high for memory accesses, or low for S1D13504 register accesses. On CPUs which implement memory-mapped IO, this pin is typically tied to an address line; on CPUs with separate IO spaces, this pin is typically driven by control logic from the CPU.

WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is writing data to the S1D13504.

RD# and RD1# are read enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is reading data from the S1D13504.

WAIT# is a signal which is output from the S1D13504 to the host CPU which indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the S1D13504 may occur asynchronously to the display update, it is possible that contention may occur in access to the 13504 internal registers and/or refresh memory. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. This signal is active low and needs to be inverted using MD5 since the MCF5307 wait state signal is active high.

The Bus Status (BS#) signal is unused in general purpose bus mode, and should be tied high (connected to IO VDD).

S1D13504

Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor

X19A-G-011-07

Issue Date: 01/02/02

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Epson S1D13504 manual Generic MPU Host Bus Interface Signals