Page 88 Epson Research and Development
Vancouver Design Center
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory cloc k]/3, [m emory cl ock]/ 4 (see R EG[19 h] bits [1:0])
2. t6min = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts
3. t7min = [((REG[07h] bits [3:0])+1)*8] Ts
4. t8 min = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [6:0])+1)] lines
5. t9min = [((REG[0Ch] bits [2:0])+1)] lines
6. t10min = [((REG[04h] bits [6:0])+1)*8] Ts
7. t12min = [((REG[06h] bits [4:0])+1)*8] Ts
8. t14min = [((REG[04h] bits [6:0])+1)*8] Ts
9. t15min = [((REG[06h] bits [4:0])+1)*8 - 2] Ts
Table 7-29: CRT A.C. Timing
Symbol Parameter Min Typ Max Units
t1 DACCLK period 1 Ts (note 1)
t2 DACCLK pulse width high 0.45 Ts
t3 DACCLK pulse width low 0.45 Ts
t4 data setup to DACCLK rising edge 0.45 Ts
t5 data hold from DACCLK rising edg e 0.45 Ts
t6 HRTC cycle time note 2
t7 HRTC pulse width (shown active low) note 3
t8 VRTC cycle time note 4
t9 VRTC pulse width (shown active low) note 5
t10 horizontal display period note 6
t11 HRTC setup to DACCLK rising edge 0.45 Ts
t12 VRTC falling edge to FPLINE falling edge
phase difference note 7
t13 BLANK# to DACCLK rising edge setup time 0.45 Ts
t14 BLANK# pulse width note 8
t15 BLANK# falling edge to HRTC falling edge note 9
t16 BLANK# hold from DACCLK rising edge 0.45 Ts