Epson S1D13504 manual Cs#, Busclk, Bs#, Rd/Wr#, Rd#

Epson Research and Development	Page 23
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Table 5-1: Host Interface Pin Descriptions (Continued)

		Pin #			Reset =
Pin Name	Type			Driver		Description
		F00A
			F02A		0 Value
		F01A
						This pin has multiple functions.
						• For SH-3 mode, this pin inputs the write enable signal for the
						upper data byte (WE1#).
						• For MC68K Bus 1, this pin inputs the upper data strobe
WE1#	I	9	11	CS	Hi-Z	(UDS#).
						• For MC68K Bus 2, this pin inputs the data strobe (DS#).
						• For Generic Bus, this pin inputs the write enable signal for the
						upper data byte (WE1#).
						See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
						This input pin is used to select between the memory and register
						address spaces of the S1D13504. M/R# is set high to access the
M/R#	I	5	7	C	Hi-Z	memory and low to access the registers. See Section 8.1,
						“Register Mapping”on page 90.
						See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
CS#	I	4	6	C	Hi-Z	Chip select input. See Table 5-9: “Host Bus Interface Pin
						Mapping,” on page 32.
BUSCLK	I	108	122	C	Hi-Z	System bus clock. See Table 5-9: “Host Bus Interface Pin
						Mapping,” on page 32.
						This pin has multiple functions.
						• For SH-3 mode, this pin inputs the bus start signal (BS#).
BS#	I	6	8	CS	Hi-Z	• For MC68K Bus 1, this pin inputs the address strobe (AS#).
						• For MC68K Bus 2, this pin inputs the address strobe (AS#).
						• For Generic Bus, this pin must be tied to IO VDD.
						See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
						This pin has multiple functions.
						• For SH-3 mode, this pin inputs the RD/WR# signal. The
						S1D13504 needs this signal for early decode of the bus cycle.
RD/WR#	I	10	12	CS	Hi-Z	• For MC68K Bus 1, this pin inputs the R/W# signal.
						• For MC68K Bus 2, this pin inputs the R/W# signal.
						• For Generic Bus, this pin inputs the read command for the
						upper data byte (RD1#).
						See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.
						This pin has multiple functions.
						• For SH-3 mode, this pin inputs the read signal (RD#).
RD#	I	7	9	CS	Hi-Z	• For MC68K Bus 1, this pin must be tied to IO VDD.
						• For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1).
						• For Generic Bus, this pin inputs the read command for the
						lower data byte (RD0#).
						See Table 5-9: “Host Bus Interface Pin Mapping,” on page 32.

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18