Epson S1D13504 5.2 Hardware DescriptionUsing Two IT8368Es

Page 16 Epson Research and Development
Vancouver Design Center
S1D13504 Interfacing to the Toshiba MIPS TX3912 Processor
X19A-G-012-04 Issue Date: 01/02/02
The Generic MPU host interface control signals of the S1D13504 are asynchronous with
respect to the S1D13504 bus clock. This gives the system designer full flexibility in
choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether
both clocks should be the same and whether to use DCLKOUT (divided) as the clock
source, should be based on the desired:
•pixel and frame rates.
•power budget.
•part count.
•maximum S1D13504 clock frequencies.
The S1D13504 also has internal clock dividers providing additional flexibility.
5.2 Hardware Description—Using Two IT8368E’s
The following implementation uses a second IT8368E, not in VGA mode, in place of an
address latch. The pins LHA23 and LHA[20:13] provide the latch function instead.