Epson manual S1D13504 Hardware Configuration

Epson Research and Development	Page 13
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4.3 S1D13504 Hardware Configuration

The S1D13504 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Specification, document number X19A-A-002-xx.

The partial table below shows those configuration settings relevant to the direct connection implementation.

Table 4-1: S1D13504 Configuration for Direct Connection

S1D13504	value on this pin at rising edge of RESET# is used to configure:(1/0)
Pin Name
	1	0
MD0	8-bit host bus interface	16-bit host bus interface
MD1
MD2	See “Host Bus Selection” table below	See “Host Bus Selection” table below
MD3
MD4	Little Endian	Big Endian
MD5	WAIT# signal is active high	WAIT# signal is active low
	= required configuration for direct connection with TX3912

Table 4-2: S1D13504 Host Bus Selection for Direct Connection

MD3	MD2	MD1	Host Bus Interface
0	0	0	SH-3 bus interface
0	0	1	MC68K bus 1 interface (e.g. MC68000)
0	1	0	MC68K bus 2 interface (e.g. MC68030)
0	1	1	Generic bus interface (e.g. MCF5307, ISA bus interface)
1	x	x	Reserved
	= required configuration for direct connection with TX3912

Interfacing to the Toshiba MIPS TX3912 Processor	S1D13504
Issue Date: 01/02/02	X19A-G-012-04