Epson S1D13504 Fpline pulse width Fpline period, FPSHIFT2 falling edge to Fpline rising edge

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	Vancouver Design Center

Sync Timing

	FPFRAME
	FPLINE
Data Timing	FPLINE

FPSHIFT

FPSHIFT2

UD[3:0]

LD[3:0]

	t1
	t2
	t3	t4
t5a
t5b	t6		t7
t8a	t9	t10	t11
t8b
	t12	t13
	1		2

Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1)

Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1)

Symbol	Parameter	Min	Typ	Max	Units
t1	FPFRAME setup to FPLINE falling edge	note 2
t2	FPFRAME hold from FPLINE falling edge	9			Ts (note 1)
t3	FPLINE pulse width	9			Ts
t4	FPLINE period	note 3
t5a	FPSHIFT2 falling edge to FPLINE rising edge	note 4
t5b	FPSHIFT falling edge to FPLINE rising edge	note 5
t6	FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge	t14 + 2			Ts
t7	FPSHIFT2, FPSHIFT period	4			Ts
t8a	FPSHIFT falling edge to FPLINE falling edge	note 6
t8b	FPSHIFT2 falling edge to FPLINE falling edge	note 7
t9	FPLINE falling edge to FPSHIFT rising edge	18			Ts
t10	FPSHIFT2, FPSHIFT pulse width high	2			Ts
t11	FPSHIFT2, FPSHIFT pulse width low	2			Ts
t12	UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge	1			Ts
t13	UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge	1			Ts
1. Ts	= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

2.t1min = t4min - 9Ts

3.	t4min	= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts
4.	t5min	= [((REG[05h] bits [4:0]) + 1)*8 - 27]+T11 Ts
5.	t5min	= [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts
6.	t8min	= [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts
7.	t8min	= [((REG[05h] bits [4:0]) + 1)*8 - 18]+T11 Ts

S1D13504	Hardware Functional Specification
X19A-A-002-18	Issue Date: 01/01/30