Page 86

Epson Research and Development

 

Vancouver Design Center

 

 

7.4.13 CRT Timing

Example Timing for 640x480 CRT

 

 

VNDP

VDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VRTC

HRTC

DACP[7:0] LINE480

BLANK#

HRTC

HNDP1

LINE1 LINE480

HDPHNDP2

DACCLK

BLANK#

DACD[7:0]

 

 

1-1

 

1-2

 

 

 

 

 

 

 

 

 

 

 

1-640

 

 

 

 

 

 

 

Figure 7-39: CRT Timing

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

VNDP

= Vertical Non-Display Period

= (REG[0Ah] bits [5:0]) + 1

HDP

= Horizontal Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

HNDP

= Horizontal Non-Display Period

= HNDP1 + HNDP2 = ((REG[05h] bits [4:0]) + 1)*8Ts

S1D13504

Hardware Functional Specification

X19A-A-002-18

Issue Date: 01/01/30

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Image 92
Epson S1D13504 manual CRT Timing