Epson S1D13504 - page 112

Page 106 Epson Research and Development
Vancouver Design Center
S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
bit 7 GPIO7 Pin IO Status
When GPIO7 is configured as an output, a “1” in this bit drives GPIO7 to high and a “0” in this bit
drives GPIO7 to low. When GPIO7 is configured as an input, a read from this bit returns the status
of GPIO7. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO7, other-
wise the DACWR# pin is controlled automatically and this bit will have no effect on hardware.
bit 6 GPIO6 Pin IO Status
When GPIO6 is configured as an output, a “1” in this bit drives GPIO6 to high and a “0” in this bit
drives GPIO6 to low. When GPIO6 is configured as an input, a read from this bit returns the status
of GPIO6. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO6, other-
wise the DACP0 pin is controlled automatically and this bit will have no effect on hardware.
bit 5 GPIO5 Pin IO Status
When GPIO5 is configured as an output, a “1” in this bit drives GPIO5 to high and a “0” in this bit
drives GPIO5 to low. When GPIO5 is configured as an input, a read from this bit returns the status
of GPIO5. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO5, other-
wise the BLANK# pin is controlled automatically and this bit will have no effect on hardware.
bit 4 GPIO4 Pin IO Status
When GPIO4 is configured as an output, a “1” in this bit drives GPIO4 to high and a “0” in this bit
drives GPIO4 to low. When GPIO4 is configured as an input, a read from this bit returns the status
of GPIO4. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO4, other-
wise the DACRD# pin is controlled automatically and this bit will have no effect on hardware.
bit 3 GPIO3 Pin IO Status
When GPIO3 is configured as an output, a “1” in this bit drives GPIO3 to high and a “0” in this bit
drives GPIO3 to low. When GPIO3 is configured as an input, a read from this bit returns the status
of GPIO3. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to
enable GPIO3, otherwise the MA9 pin is controlled automatically and this bit will have no effect on
hardware.
bit 2 GPIO2 Pin IO Status
When GPIO2 is configured as an output, a “1” in this bit drives GPIO2 to high and a “0” in this bit
drives GPIO2 to low. When GPIO2 is configured as an input, a read from this bit returns the status
of GPIO2. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to
enable GPIO2, otherwise the MA11 pin is controlled automatically and this bit will have no effect
on hardware.
bit 1 GPIO1 Pin IO Status
When GPIO1 is configured as an output, a “1” in this bit drives GPIO1 to high and a “0” in this bit
drives GPIO1 to low. When GPIO1 is configured as an input, a read from this bit returns the status
of GPIO1. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to
enable GPIO1, otherwise the MA10 pin is controlled automatically and this bit will have no effect
on hardware.
bit 0 GPIO0 Pin IO Status
When GPIO0 is configured as an output, a “1” in this bit drives GPIO0 to high and a “0” in this bit
drives GPIO0 to low. When GPIO0 is configured as an input, a read from this bit returns the status
of GPIO0.
GPIO Status / Control Register 0
REG[20h] RW
GPIO7 Pin
IO Status GPIO6 Pin IO Status GPIO5 Pin IO Status GPIO4 Pin IO Status GPIO3 Pin IO Status GPIO2 Pin IO Status GPIO1 Pin IO Status GPIO0 Pin IO Status