Page 94

Epson Research and Development

 

Vancouver Design Center

 

 

HRTC/FPLINE Pulse Width Register

 

 

 

 

 

 

 

 

 

 

REG[07h]

 

 

 

 

 

 

 

 

 

 

 

 

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HRTC

FPLINE

 

 

 

 

 

 

HRTC/

 

HRTC/

HRTC/

HRTC/

Polarity

Polarity

 

n/a

 

 

n/a

 

FPLINE Pulse

 

FPLINE Pulse

FPLINE Pulse

FPLINE Pulse

Select

Select

 

 

 

 

 

 

Width Bit 3

 

Width Bit 2

Width Bit 1

Width Bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bit 7

 

HRTC Polarity Select

 

 

 

 

 

 

 

 

 

 

For CRTs, this bit selects the polarity of the HRTC. When this bit = 1, the HRTC pulse is active

 

 

 

high. When this bit = 0, the HRTC pulse is active low.

 

 

 

bit 6

 

FPLINE Polarity Select

 

 

 

 

 

 

 

 

 

 

This bit selects the polarity of the FPLINE for TFT and passive LCD. When this bit = 1, the

 

 

 

FPLINE pulse is active high for TFT and active low for passive LCD. When this bit = 0, the

 

 

 

FPLINE pulse is active low for TFT and active high for passive LCD.

 

 

 

 

 

 

 

Table 8-4: FPLINE Polarity Selection

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPLINE Polarity Select

 

 

Passive LCD FPLINE Polarity

 

TFT FPLINE Polarity

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

active high

 

active low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

active low

 

active high

 

 

 

 

 

 

 

 

 

 

 

 

bits 3-0

 

HRTC/FPLINE Pulse Width Bits [3:0]

 

 

 

 

 

 

 

 

For CRTs and TFTs, these bits specify the pulse width of HRTC and FPLINE respectively. For pas-

 

 

 

sive LCDs, FPLINE is automatically created and these bits have no effect.

 

 

 

 

 

HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) 8.

The maximum HRTC pulse width is 128 pixels.

Note

This register must be programmed such that

(REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)

Vertical Display Height Register 0

 

 

 

 

 

REG[08h]

 

 

 

 

 

 

RW

 

 

 

 

 

 

 

 

Vertical

Vertical

Vertical

Vertical

Vertical

Vertical

Vertical

Vertical

Display

Display

Display

Display

Display

Display

Display

Display

Height Bit 7

Height Bit 6

Height Bit 5

Height Bit 4

Height Bit 3

Height Bit 2

Height Bit 1

Height Bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vertical Display Height Register 1

 

 

 

 

 

REG[09h]

 

 

 

 

 

 

RW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vertical

Vertical

n/a

n/a

n/a

n/a

n/a

n/a

Display

Display

 

 

 

 

 

 

Height Bit 9

Height Bit 8

 

 

 

 

 

 

 

 

REG[08h] bits 7-0

Vertical Display Height Bits [9:0]

REG[09h] bits 1-0

These bits specify the LCD panel and/or the CRT vertical display height, in 1-line resolution. For a

 

dual LCD panel only configuration, this register should be programmed to half the panel size.

 

Vertical display height in number of lines = (ContentsOfThisRegister) + 1.

 

The maximum vertical display height is 1024 lines.

S1D13504

Hardware Functional Specification

X19A-A-002-18

Issue Date: 01/01/30

Page 100
Image 100
Epson S1D13504 manual HRTC/FPLINE Pulse Width Register, Vertical Display Height Register, Hrtc Fpline