Epson S1D13504 manual Block Description, Functional Block Diagram, Memory Controller, Display Fifo

Epson Research and Development	Page 17
Vancouver Design Center

4 Block Description

4.1 Functional Block Diagram

	16-bit FPM/EDO
	DRAM
Register	Memory	Power Save
	Controller
		Clocks
	CPU	LCD	LCD
	R/W
Host	Display	I/F	DAC
CPU / MPU	FIFO		Data
I/F		Look-Up
		Table
			DAC
			Control
		CRTC
Bus Clock	Memory Clock	Pixel Clock

Figure 4-1: System Block Diagram Showing Datapaths

4.2 Functional Block Descriptions

4.2.1 Host Interface

The Host Interface block provides the means for the CPU/MPU to communicate with the display buffer and internal registers, via one of the supported bus interfaces.

4.2.2 Memory Controller

The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well as generates the necessary signals to interface to one of the supported 16-bit memory devices (FPM- DRAM or EDO-DRAM).

4.2.3 Display FIFO

The Display FIFO block fetches display data from the Memory Controller for display refresh.

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18