Epson S1D13504 - page 74

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S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
Figure 7-22: Single Monochrome 8-Bit Panel A.C. Timing
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory cloc k]/3, [m emory cl ock]/ 4 (see R EG[19 h] bits [1:0])
2. t1min = t4min - 9Ts
3. t4min = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
4. t5min = [((REG[04h] bits [6:0]) + 1)*8 - 1] Ts
5. t6min = [((REG[05h] bits [4:0]) + 1)*8 - 23] Ts
6. t9min = [((REG[05h] bits [4:0]) + 1)*8 - 14] Ts
Table 7-20: Single Monochrome 8-Bit Pane l A.C. Timing
Symbol Parameter Min Typ Max Units
t1 FPFRAME setup to FPLINE falling edge note 2
t2 FPFRAME hold from FPLINE falling edge 9 Ts (note 1)
t3 FPLINE pulse width 9Ts
t4 FPLINE period note 3
t5 MOD transition to FPLINE falling edge 33 note 4 Ts
t6 FPSHIFT falling edge to FPLINE rising edge note 5
t7 FPLINE falling edge to FPSHIFT falling edge t14 + 4 Ts
t8 FPSHIFT period 8Ts
t9 FPSHIFT falling edge to FPLINE falling edge note 6
t10 FPLINE falling edge to FPSHIFT rising edge 18 Ts
t11 FPSHIFT pulse width high 4Ts
t12 FPSHIFT pulse width low 4Ts
t13 UD[3:0], LD[3:0] setup to FPSHIFT falling edge 4Ts
t14 UD[3:0], LD[3:0] hold to FPSHIFT falling edge 4Ts
t13 t14
FPFRAME
FPLINE
MOD
Sync Timing
FPLINE
FPSHIFT
UD[3:0]
LD[3:0]
Data Timing
t5
t1 t2
t4
t3
t10
t7 t8
t12t11
12
t9
t6