Page 14

Epson Research and Development

 

Vancouver Design Center

 

 

Table 3-2: Connector Pinout for Channel A7 (Continued)

Channel A7

Pin #

FPGA Signal

S1D13504 Signal

 

Pin #

FPGA Signal

S1D13504 Signal

 

 

 

 

 

 

 

 

 

SmZ

 

 

 

 

 

 

 

 

 

 

1

chA7p11

N/C

 

21

GND

GND

2

chA7p12

N/C

 

22

GND

GND

 

 

 

 

 

 

 

3

chA7p13

A20

 

23

chA7p34

A19

4

chA7p14

A18

 

24

GND

GND

 

 

 

 

 

 

 

5

chA7p15

A17

 

25

GND

GND

6

chA7p16

A16

 

26

GND

GND

 

 

 

 

 

 

 

7

chA7p17

N/C

 

27

chA7p33

A15

8

chA7p18

A14

 

28

GND

GND

 

 

 

 

 

 

 

9

chA7p19

A13

 

29

GND

GND

10

chA7p20

A12

 

30

GND

GND

 

 

 

 

 

 

 

11

chA7p21

A11

 

31

chA7p32

A10

12

chA7p22

A9

 

32

GND

GND

 

 

 

 

 

 

 

13

chA7p23

A8

 

33

GND

GND

14

chA7p24

A7

 

34

GND

GND

 

 

 

 

 

 

 

15

chA7p25

A6

 

35

GND

GND

16

chA7p26

A5

 

36

chA7p31

A4

 

 

 

 

 

 

 

17

chA7p27

A3

 

37

GND

GND

18

chA7p28

A2

 

38

GND

GND

 

 

 

 

 

 

 

19

chA7p29

A1

 

39

GND

GND

20

chA7p30

A0

 

40

GND

GND

 

 

 

 

 

 

 

S5U13504-D9000

Evaluation Board User Manual

X19A-G-003-05

Issue Date: 01/02/02

Page 346
Image 346
Epson manual Channel A7 Pin # Fpga Signal S1D13504 Signal SmZ