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Epson Research and Development

Vancouver Design Center

7 A.C. Characteristics

Conditions: IO VDD = 2.7V to 5.5V unless otherwise specified

TA = -40°C to 85° C

Trise and Tfall for all inputs must be 5 nsec (10% ~ 90%)

CL = 50pF (Bus / MPU Interface)

CL = 100pF (LCD Panel Interface)

CL = 10pF (Display Buffer Interface)

CL = 10pF (CRT / DAC Interface)

7.1 CPU Interface Timing

7.1.1 SH-3 Interface Timing

t1

t2

t3

 

 

CKIO

 

 

 

 

 

t4

 

 

t5

A[20:0], M/R#

 

 

 

 

RD/WR#

 

 

 

 

 

t6

t7

 

 

BS#

 

 

 

 

 

t8

t12

 

 

CSn#

 

 

 

 

 

 

t9

 

t10

WEn#

 

 

 

 

RD#

 

 

 

 

 

 

t11

t12

 

WAIT#

 

 

 

 

 

 

t13

 

t14

D[15:0](write)

 

 

 

 

 

 

 

t15

t16

D[15:0](read)

 

 

 

 

 

 

 

Figure 7-1: SH-3 Interface Timing

 

Note

The SH-3 Wait State Control Register for the area in which the S1D13504 resides must be set to a non-zero value.

S1D13504

Hardware Functional Specification

X19A-A-002-18

Issue Date: 01/01/30

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Image 42
Epson S1D13504 manual CPU Interface Timing 1 SH-3 Interface Timing, Rd/Wr# Bs#, Wait#