Epson Research and Development

Page 63

Vancouver Design Center

7.4 Display Interface

7.4.1

Power-On/Reset Timing

 

 

 

 

TRESET#

 

 

 

 

RESET#

 

 

 

 

LCD ENABLE

 

 

 

 

(REG[0Dh] bit 0)

 

 

 

 

LCDPWR

 

Inactive

Active

 

FPFRAME

 

 

Active

 

 

 

 

 

FPLINE

 

 

Active

 

FPSHIFT

 

 

 

 

 

 

 

FPDAT[15:0]

t1

 

t2

 

DRDY

 

 

 

 

 

Figure 7-17: LCD Panel Power-On/Reset Timing

Table 7-17: LCD Panel Power-On/Reset Timing

Symbol

Parameter

Min

Typ

Max

Units

TRESET#

RESET# pulse time

100

 

 

us

t1

LCD Enable bit high to FPLINE, FPSHIFT, FPDAT[15:0], DRDY

 

 

TFPFRAME + 6TPCLK

ns

active

 

 

 

 

 

 

 

 

 

 

 

 

 

t2

FPLINE, FPSHIFT, FPDAT[15:0], DRDY active to LCDPWR, on

 

128

 

Frames

and FPFRAME active

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock.

Hardware Functional Specification

S1D13504

Issue Date: 01/01/30

X19A-A-002-18

Page 69
Image 69
Epson S1D13504 manual Display Interface Power-On/Reset Timing, Fpframe active