Epson Research and Development

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Vancouver Design Center

2.1.2 LCD Memory Access Cycles

Once an address in the LCD block of memory is placed on the external address bus (ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle. The high byte enable (SHB#) is driven low for 16-bit transfers and high for 8-bit transfers.

The following figure illustrates typical NEC VR4102 memory read and write cycles to the LCD controller interface.

TCLK

 

 

 

ADD[25:0]

VALID

 

 

SHB#

 

 

 

LCDCS#

 

 

 

WR#,RD#

 

 

 

D[15:0]

VALID

 

 

(write)

 

 

 

 

 

D[15:0]

Hi-Z

VALID

Hi-Z

(read)

 

 

 

 

 

LCDRDY

 

 

 

 

Figure 2-1: NEC VR4102 Read/Write Cycles

 

 

Interfacing to the NEC VR4102™ Microprocessor

S1D13504

Issue Date: 01/02/02

X19A-G-007-07

Page 393
Image 393
Epson S1D13504 manual LCD Memory Access Cycles, Lcdrdy