Epson S1D13504 manual Sync Timing, Data Timing

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	Vancouver Design Center

Sync Timing

FPFRAME

FPLINE

MOD

Data Timing

FPLINE

FPSHIFT

UD[3:0]

t1	t2
t3	t4

t5

t6

		t7					t8
t9	t10				t11			t12
			t13	t14
		1				2

Figure 7-20: Single Monochrome 4-Bit Panel A.C. Timing

Table 7-19: Single Monochrome 4-Bit Panel A.C. Timing

Symbol		Parameter	Min	Typ	Max	Units
t1		FPFRAME setup to FPLINE falling edge	note 2
t2		FPFRAME hold from FPLINE falling edge	9			Ts (note 1)
t3		FPLINE pulse width	9			Ts
t4		FPLINE period	note 3
t5		MOD transition to FPLINE falling edge	33		note 4	Ts
t6		FPSHIFT falling edge to FPLINE rising edge	note 5
t7		FPLINE falling edge to FPSHIFT falling edge	t14 + 2			Ts
t8		FPSHIFT period	4			Ts
t9		FPSHIFT falling edge to FPLINE falling edge	note 6
t10		FPLINE falling edge to FPSHIFT rising edge	18			Ts
t11		FPSHIFT pulse width high	2			Ts
t12		FPSHIFT pulse width low	2			Ts
t13		UD[3:0] setup to FPSHIFT falling edge	2			Ts
t14		UD[3:0] hold to FPSHIFT falling edge	2			Ts
1. Ts	= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

2.t1min = t4min - 9Ts

3.	t4min	= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
4.	t5min	= [((REG[04h] bits [6:0]) + 1)*8 - 1] Ts
5.	t6min	= [((REG[05h] bits [4:0]) + 1)*8 - 25] Ts
6.	t9min	= [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts

S1D13504	Hardware Functional Specification
X19A-A-002-18	Issue Date: 01/01/30