Epson Research and Development

Page 9

Vancouver Design Center

 

 

 

List of Figures

Figure 3-1:

Typical System Diagram – SH-3 Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . . . . . . . 14

Figure 3-2:

Typical System Diagram – MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000) . . . . 15

Figure 3-3:

Typical System Diagram – MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030) . . 15

Figure 3-4:

Typical System Diagram – Generic Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . . . . . 16

Figure 4-1:

System Block Diagram Showing Datapaths

17

Figure 5-1:

Pinout Diagram of F00A

19

Figure 5-2:

Pinout Diagram of F01A

20

Figure 5-3:

Pinout Diagram of F02A

21

Figure 7-1:

SH-3 Interface Timing

36

Figure 7-2:

MC68K Bus 1 Interface Timing

38

Figure 7-3:

MC68K Bus 2 Interface Timing

40

Figure 7-4:

Generic MPU Interface Synchronous Timing

42

Figure 7-5:

Generic MPU Interface Asynchronous Timing

44

Figure 7-6:

Clock Input Requirements

46

Figure 7-7:

EDO-DRAM Read Timing

47

Figure 7-8:

EDO-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 7-9:

EDO-DRAM Read-Write Timing

51

Figure 7-10:

EDO-DRAM CAS Before RAS Refresh Timing

53

Figure 7-11:

EDO-DRAM Self-Refresh Timing

54

Figure 7-12:

FPM-DRAM Read Timing

55

Figure 7-13:

FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 7-14:

FPM-DRAM Read-Write Timing

59

Figure 7-15:

FPM-DRAM CAS# Before RAS# Refresh Timing

61

Figure 7-16:

FPM-DRAM CBR Self-Refresh Timing

62

Figure 7-17:

LCD Panel Power-On/Reset Timing

63

Figure 7-18:

LCD Panel Suspend Timing

64

Figure 7-19:

Single Monochrome 4-Bit Panel Timing

65

Figure 7-20:

Single Monochrome 4-Bit Panel A.C. Timing

66

Figure 7-21:

Single Monochrome 8-Bit Panel Timing

67

Figure 7-22:

Single Monochrome 8-Bit Panel A.C. Timing

68

Figure 7-23:

Single Color 4-Bit Panel Timing

69

Figure 7-24:

Single Color 4-Bit Panel A.C. Timing

70

Figure 7-25:

Single Color 8-Bit Panel Timing (Format 1)

71

Figure 7-26:

Single Color 8-Bit Panel A.C. Timing (Format 1)

72

Figure 7-27:

Single Color 8-Bit Panel Timing (Format 2)

73

Figure 7-28:

Single Color 8-Bit Panel A.C. Timing (Format 2)

74

Figure 7-29:

Single Color 16-Bit Panel Timing

75

Figure 7-30:

Single Color 16-Bit Panel A.C. Timing

76

Figure 7-31:

Dual Monochrome 8-Bit Panel Timing

77

Figure 7-32:

Dual Monochrome 8-Bit Panel A.C. Timing

78

Hardware Functional Specification

S1D13504

Issue Date: 01/01/30

X19A-A-002-18

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Epson S1D13504 manual List of Figures