Epson S1D13504 manual External Ramdac Read / Write Timing, DACWR# pulse width low

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7.4.14 External RAMDAC Read / Write Timing

Read	t2
t1
AB[20:0]
CS#
M/R#
DACRS[1:0]
Valid RD# Command
(depends on CPU bus)
t3	t4
DACRD#
Write
Valid WR# command
(depends on CPU bus)
	t5
DACWR#
	t6

Figure 7-41: Generic Bus RAMDAC Read / Write Timing

Table 7-30: Generic Bus RAMDAC Read / Write Timing

Symbol	Parameter	Min	Typ	Max	Units
TBCLK	Bus clock period	30			ns
t1	AB[20:0], CS#, M/R# delay to DACRS[1:0]			10	ns
t2	DACRS[1:0] hold from AB[20:0], CS#, M/R# negated			10	ns
t3	Valid RD# command to DACRS[1:0] delay	8		33	ns
t4	DACRD# hold from valid RD# command negated	3		14	ns
t5	Valid WR# command to DACWR# delay	2 TBCLK			ns
t6	DACWR# pulse width low	2.45 TBCLK		2.55 TBCLK	ns

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18