Epson Research and Development Page 109
Vancouver Design Center
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
Note that for EDO-DRAM and NRP = 1.5, this bit is automatically forced to 0 to select 2 MCLK for
NRCD. This is done to satisfy the CAS# address setup time, tASC.
The resulting tRC is related to NRCD as follows:
tRC = (NRCD) TMif EDO and NRP = 1 or 2
tRC = (1.5) TMif EDO and NRP = 1.5
tRC = (NRCD + 0.5) TMif FPM and NRP = 1 or 2
tRC = (NRCD) TMif FPM and NRP = 1.5
bits 3-2 RAS# Precharge Timing (NRP) Bits [1:0]
Minimum Memory Timing for RAS precharge
These bits select the DRAM RAS# Precharge timing parameter, tRP. These bits specify the number
(NRP) of MCLK periods (TM) used to create tRP - see the following formulae. Note, these formulae
assume an MCLK duty cycle of 50 +/- 5%.
NRP = 1 if (tRP/TM) < 1
= 1.5 if 1 ≤ (tRP/TM) < 1.45
= 2 if (tRP/TM) ≥ 1.45
The resulting tRC is related to NRP as follows:
tRC = (NRP + 0.5) TMif FPM refresh cycle and NRP = 1 or 2
tRC = (NRP) TMfor all other
Optimal DRAM Timing
The following table contains the optimally programmed values of NRC, NRP, and NRCD for different
DRAM types, at maximum MCLK frequencies.
bit 0 Reserved
Must be set to 0.
Table 8-12: RAS-to-CAS Delay Timing Select
REG[22h] Bit 4 NRCD RAS# to CAS# Delay (tRCD)
022 T
M
111 T
M
Table 8-13: RAS Precharge Timing Select
REG[22h] Bits [3:2] NRP RAS# Precharge Width (tRP)
00 2 2 TM
01 1.5 1.5 TM
10 1 1 TM
11 Reserved Reserved
Table 8-14: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency
DRAM Type DRAM Speed
(ns) TM
(ns) NRC
(#MCLK) NRP
(#MCLK) NRCD
(#MCLK)
EDO 50 25 4 1.5 2
60 30 4 1.5 2
70 33 5 2 2
FPM 60 40 4 1.5 2
70 50 3 1.5 1