Epson S1D13504 manual Bus Interface Timing, Memory Address CS#, M/R# Decode, Makefpga file

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3.1.2 Bus Interface Timing

Refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx for complete bus timing details.

Note

Afour-position DIP switch located on the S5U13504-D9000 allows for the following configura- tions.

Table 3-4: DIP Switch Configuration

SW4	SW3	SW2	SW1	Function
x	0	0	0	SH-3 Bus Interface
x	0	0	1	MC68K Bus
				1 Interface
x	0	1	0	MC68K Bus
				2 Interface
x	0	1	1	Generic Bus Interface
0	x	x	x	WAIT# - active low
1	x	x	x	WAIT# - active high

Where 1 = closed/on and 0 = open/off

3.1.3 Memory Address (CS#, M/R#) Decode

The S1D13504 is a memory-mapped device for both the registers and display buffer access. The specific memory address is solely controlled by the CS# and M/R# decode logic. The memory space requirements are:

•a 2M byte linear address range for the display buffer

•47 bytes for the registers.

3.1.4Makefpga file

Modifications to the makefpga file to accommodate the S1D13504 are:

1.Bus model: this may differ depending on processor as far as interface requirements (signal def- initions). Epson will provide this information for each given processor interface.

2.Memory location: the system designer must determine the appropriate memory addresses for the display buffer and register requirements.

3.2Board Dimensions

To obtain the required number of interface signals, the S5U13504-D9000 utilizes two SmallTypeZ slots (6 and 7). Board dimensions are 2.65x3.20 with both the CRT and LCD connectors accessible on the outside edge.

3.3 Support Documentation Notes

Note that some files and/or documentation may refer to the S5U13504-D9000 as the S5U13504- D9100.

Evaluation Board User Manual	S5U13504-D9000
Issue Date: 01/02/02	X19A-G-003-05