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Epson S1D13504 manual Introduction

Models: S1D13504

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Epson Research and Development	Page 7
Vancouver Design Center

1 Introduction

This application note describes the hardware and software environment required to provide an interface between the S1D13504 Color Graphics LCD/CRT Controller and the PC Card (PCMCIA) bus.

The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America Website at http://www.eea.epson.com for the latest revision of this document before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at techpubs@erd.epson.com.

Interfacing to the PC Card Bus	S1D13504
Issue Date: 01/02/02	X19A-G-009-05

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Epson S1D13504 manual Introduction

Contents

Document Number X19A-Q-002-14 Technical ManualThis page Left Blank Customer Support Information This page Left Blank General Purpose IO pins Power Down ModesMemory Interface CPU InterfaceRamdac CPUDocument Number X19A-A-002-18 Hardware Functional SpecificationX19A-A-002-18 Issue Date 01/01/30 Table of Contents Registers Power Save Modes 128 Display Configuration 116Display Buffer Clocking 119This page Left Blank List of Tables Vancouver Design Center List of Figures Vancouver Design Center Scope IntroductionOverview Description Memory Interface FeaturesCPU Interface Display SupportClock Source Display ModesMiscellaneous Package and PinLCD Typical System Implementation DiagramsManagement MC68000 Typical System Diagram Generic Bus, 1Mx16 FPM/EDO-DRAM Block Description Functional Block DiagramFunctional Block Descriptions Host Interface Memory ControllerLook-Up Table Power SaveLCD Interface Pin Out Pinout Diagram for S1D13504F00APackage type 128 pin surface mount QFP15 Package type 128 pin surface mount TQFP15 Pinout Diagram for S1D13504F01APackage type 144 pin surface mount QFP20 Pinout Diagram for S1D13504F02AKey Pin DescriptionAB0 TS2Busclk CS#BS# RD/WR#WAIT# TS2 RESET#UCAS# CO1 LCAS# CO1WE# CO1 RAS# CO1MA9 TS1 LCD Interface Pin Descriptions Clock InputCRT and External Ramdac Interface Hrtc CRT and Ramdac Interface Pin DescriptionsVrtc BLANK# CN3Pin # Pin Name Type Driver Description F00A F02A F01A Power SupplySummary of Configuration Options S1D13504 SH-3 MC68K Bus Generic MPU Pin Names Multiple Function Pin MappingAsym 256Kx16 Asym 1Mx1611 LCD, CRT, Ramdac Interface Pin Mapping Symbol Parameter Rating Units C. CharacteristicsSymbol Parameter Condition Min Typ Max Units Output Leakage Current Low Level Output VoltageOutput Pin Capacitance Bidirectional Pin CapacitanceRD/WR# BS# CPU Interface Timing 1 SH-3 Interface TimingWAIT# Symbol Parameter Min Max Units AS# UDS# LDS# 2 MC68K Bus 1 Interface Timing e.g. MC68000T13 T14 T15 D150read AS# high to DTACK# high impedance AS# high setup to CLKD150 hold from falling edge of DTACK# write cycle D150 valid to DTACK# falling edge read cycleA200 SIZ10 M/R# 3 MC68K Bus 2 Interface Timing e.g. MC68030AS# DS# T13 T14 T15D3116 valid to DSACK1# falling edge read cycle D3116 hold from falling edge of DSACK1# write cycleBclk Generic MPU Interface Synchronous TimingA200 RD0#,RD1# WE0#,WE1# Hi-ZLow write cycle D150 hold from WE0#, WE1# high write cycle A200 Valid Generic MPU Interface Asynchronous TimingHi-Z Valid T10 D150read T82 Clock Input Requirements Symbol Parameter Min Typ Max UnitsRAS# CAS# Memory Interface Timing EDO-DRAM Read TimingEDO Dram Read Timing RAS# CAS# WE# EDO-DRAM Write Timing55 t1 + CAS# precharge time 45 t1 T14 Write Data setup time 45 t1 T15 Write Data hold timeEDO-DRAM Read-Write Timing EDO-DRAM Read-Write TimingEDO Dram Read-Write Timing 10 EDO-DRAM CAS Before RAS Refresh Timing EDO-DRAM CAS Before RAS Refresh Timing11 EDO-DRAM Self-Refresh Timing EDO-DRAM Self-Refresh Timing12 FPM-DRAM Read Timing FPM-DRAM Read Timing12 FPM Dram Read Timing 13 FPM-DRAM Write Timing FPM-DRAM Write TimingT14 Write Data setup time 45 t1 T15 Write Data hold time 14 FPM-DRAM Read-Write Timing FPM-DRAM Read-Write Timing45 t1 S1D13504 RAS# precharge time REG22h bits 32 = 01 or 45 t1 FPM-DRAM CAS# Before RAS# Refresh Timing16 FPM-DRAM CBR Self-Refresh Timing FPM-DRAM Self-Refresh TimingFpframe active Display Interface Power-On/Reset TimingMclk Suspend TimingVDP = Single Monochrome 4-Bit Panel TimingVndp = HDP =Data Timing Sync TimingVDP Single Monochrome 8-Bit Panel TimingVndp HDPUD30, LD30 hold to Fpshift falling edge UD30, LD30 setup to Fpshift falling edge= REG05h bits 40 + 1*8 23 Ts = REG05h bits 40 + 1*8 14 Ts23 Single Color 4-Bit Panel Timing Single Color 4-Bit Panel Timing= REG05h bits 40 + 1*8 26 Ts = REG04h bits 60+1*8 1 Ts= REG05h bits 40 + 1*8 17 Ts 25 Single Color 8-Bit Panel Timing Format Single Color 8-Bit Panel Timing FormatFpline pulse width Fpline period UD30, LD30 setup to FPSHIFT2 rising, Fpshift falling edgeFPSHIFT2 falling edge to Fpline rising edge FPSHIFT2, Fpshift pulse width high27 Single Color 8-Bit Panel Timing Format T1min = t3min 9Ts VDP Vndp LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP Hndp Single Color 16-Bit Panel TimingUD70, LD70 hold to Fpshift falling edge UD70, LD70 setup to Fpshift falling edgeFpshift UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 Dual Monochrome 8-Bit Panel Timing= REG05h bits 40 + 1*8 8 Ts 33 Dual Color 8-Bit Panel Timing Dual Color 8-Bit Panel Timing= REG05h bits 40 + 1*8 9 Ts 35 Dual Color 16-Bit Panel Timing Dual Color 16-Bit Panel TimingUD70 LD70 = Vertical Display Period = REG09h bits 10, REG08h bits 70 + 12 16-Bit TFT Panel Timing38 TFT A.C. Timing = REG07h bits 30+1*8 Ts = REG04h bits 60+1*8 + REG05h bits 40+1*8 Ts= REG0Ch bits 20+1 lines 39 CRT Timing CRT Timing40 CRT A.C. Timing Dacclk period Read External Ramdac Read / Write TimingWrite DACWR# pulse width lowRegister Mapping RegistersRegister Descriptions Revision Code RegisterMemory Configuration Register Memory Configuration RegistersTime/256 Cycles Panel Type Register Panel/Monitor Configuration RegistersMOD Rate Register REG03h MOD Rate BitHorizontal Non-Display Period Register Horizontal Display Width RegisterHRTC/FPLINE Start Position Register Vertical Display Height Register HRTC/FPLINE Pulse Width RegisterHrtc Fpline VRTC/FPFRAME Start Position Register Vertical Non-Display Period RegisterVrtc Fpframe REG0Ch VRTC/FPFRAME Pulse Width RegisterFpframe Vrtc Vrtc PolarityDisplay Mode Register Display Configuration RegistersSimultaneous Display Option Select Bits Even Scan OnlyNumber of Bits-Per-Pixel Selection Screen 1 Display Start Address Register Screen 1 Line Compare RegisterScreen 2 Display Start Address Register Screen 2 Display Start Address Register 0 RWMemory Address Offset Register Clock Configuration Register Clock Configuration RegisterPixel Panning Register Number of Bits-Per-Pixel Screen 2 Pixel Panning Bits UsedPower Save Configuration Register Power Save Configuration RegistersMiscellaneous Disable Register Miscellaneous RegistersGpio Configuration Register MD Configuration Readback RegisterREG1Dh MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8Vancouver Design Center REG1Fh GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin IO Config Gpio Status / Control Register REG21h Gpio Status / Control RegisterGPO GPIO11 Pin GPIO10 Pin GPIO9 Pin GPIO8 Pin Control IO StatusREG22h EDO Read RC Timing RAS# to Performance Enhancement RegisterREG22h Bits Minimum Random Cycle Width t RCOptimal Dram Timing RAS# to CAS# Delay tRCDREG22h Bit RAS# Precharge Width t RPLook-Up Table Registers RGB Index Bits Look-Up Table Access Pointer SequenceLook-Up Table Address Register Look-Up Table Bank Select Register Look-Up Table Data RegisterREG26h LUT Data Bit REG27h Red Bank Blue Bank Green Bank Select BitRamdac Write Mode Address Register Ramdac Read Mode Address RegisterExternal Ramdac Control Registers Ramdac Pixel Read Mask RegisterREG2Eh or REG2Fh Ramdac Palette Data Register512K byte Memory AB200 Display BufferHalf Frame Buffer Image BufferDisplay Mode Data Format Display Configuration15/16 Bit-Per-Pixel Format Memory Organization Display Image ManipulationImage Buffer Maximum Mclk Pclk Ratios ClockingDisplay type Maximum Pclk Allowed Bpp 16 bpp= Pclk Frame Rate CalculationSpeed Grade Bpp Clock Hndpt s Panel MHzFPM-DRAM Display Mode Bit Wide Look-Up Table Bit-Per-Pixel ModeLook-Up Table Architecture Gray Shade Display ModesBit-Per-Pixel Mode Color Display Modes Bit-Per-Pixel Color ModeBank Selected Bank Entry Bit Red data output Logic Red Look-Up Table 0000 0001 0010 0011 0100 0101 Entry 0110 Color Data Format Red Look-Up Table Hardware Suspend Power Save ModesSoftware Suspend Pin States in Power Save Modes Power Save Mode Function SummaryPower Save Mode PSM Pin State Pins Normal Software Hardware Active Suspend14.1 QFP15-128 S1D13504F00A Mechanical DataQFP15 128 pin Unit mm TQFP15 128 pin Unit mm TQFP15-128 S1D13504F01A±0.2 QFP20 144 pin Unit mm QFP20-144 S1D13504F02A125 Document Number X19A-G-002-07 Programming Notes and ExamplesThis page Left Blank Introduction Programming the S1D13504 Registers LCD Power Sequencing and Power Save ModesAdvanced Techniques Identifying the S1D13504 Hardware Abstraction Layer HAL CRT ConsiderationsSample Code Appendix a Supported Panel ValuesInitializing the S1D13504 Registers This page Left Blank Introduction 2 REG22 bits 7-2 Performance Enhancement Register Programming the S1D13504 Registers3 REG02 bit 1 Dual/Single Panel Type 5 REG23 Display Fifo 4 REG1B bit 0 Half Frame Buffer DisableRegister Initialization Initialization Sequence Initializing the S1D13504 Registers Initialization ExampleOperation Description Disabling the Half Frame Buffer Sequence Re-Programming RegistersBit Display Buffer LocationPixel Bit Bit Red Bit Green Bit Blue Bit Memory Organization for Eight Bit-per-pixel 256 ColorsMemory Organization for 16 Bit-per-pixel 65536 Colors Memory Organization for 15 Bit-per-pixel 32768 ColorsBit Reserved Red Bit Green Bit Blue Bit REG24h Look-Up Table Address Register Read/Write Look-Up Table LUTREG26h Look-Up Table Data Register Read/Write REG27h Look-Up Table Bank Register Read/WriteBank Select Bits Look-Up Table Organization Look-Up Table ConfigurationsBank Recommended LUT Values for 2 bpp Color Mode Recommended LUT Values for 1 bpp Color ModeColor Modes Address Red Green Blue11 Recommended LUT Values For 8 bpp Color Mode Gray Shade Modes 12 Examples of 256 Pixel Colors Using Linear LUT13 Recommended LUT Values for 1 bpp Gray Shades Pixel Value Color15 Recommended LUT Values for 8 bpp Gray Shade 14 Recommended LUT Values for 2 bpp Gray ShadesLUT Address Green LUT Data Bpp Gray Shade Virtual Display Advanced Technique sExamples RegistersREG16h Memory Address Offset Register REG17h Memory Address Offset RegisterPanning and Scrolling Active Pixel Pan Bits Number of Pixels Panned Using Start AddressExample 4 Panning Right and Left REG0E Screen 1 Line Compare Register Split ScreenLine Compare Bit REG0F Screen 1 Line Compare RegisterREG14h Screen 2 Display Start Address Register REG13h Screen 2 Display Start Address RegisterREG15h Screen 2 Display Start Address Register Introduction to LCD Power Sequencing LCD Power Sequencing and Power Save ModesIntroduction to Power Save Modes Display Mode RegisterShortening the 128 Frame delay using Software Suspend Suspend Enable SequenceShortening the 128 Frame Delay using Hardware SUSPEND# Suspend SequencingLCD Enable/Disable Sequencing Reg0D bit Suspend Disable SequenceLCD Enable / Disable using Power Save Modes LCD Enable / Disable using Manual ControlIntroduction CRT ConsiderationsCRT Only Ramdac Register Mapping for Little/Big-EndianRelated Register Data for CRT Only Simultaneous DisplayAddress Address Register 640X480@75Hz 640X480@60Hz Related register data for Simultaneous DisplayIdentifying the S1D13504 API for 13504HAL Hardware Abstraction Layer HALInitialization Int seDeRegisterDeviceint device Int seInitHalvoid Int seGetIdint device, Byte *pIdInt seValidRegisteredDeviceint device Int seSetInitint deviceInt seValidStdDeviceint device Int seGetBytesPerScanlineint device, int *pBytes Int seGetBitsPerPixelint device, Byte *pBitsPerPixelInt seGetLastUsableByteint device, Dword *pLastByte Int seGetLinearDispAddrint device, Dword *pDispLogicalAddrInt seReadDisplayByteint device, Dword offset, Byte *pByte Int seGetScreenSizeint device, int *width, int *heightInt seReadDisplayWordint device, Dword offset, Word *pWord Int seSplitInitint device, Dword Scrn1Addr, Dword Scrn2Addr Int seSetBitsPerPixelint device, Byte BitsPerPixelInt seVirtMoveint device, Byte WhichScreen, int x, int y Int seVirtInitint device, int xVirt, long *yVirtVancouver Design Center Int seGetDacEntryint device, Byte index, Byte *pEntry Color Manipulation Int seGetDacint device, Byte *pDacInt seGetLutint device, Byte *pLut Int seSetDacint device, Byte *pDac Int seGetLutEntryint device, Byte index, Byte *pEntryInt seSetDacEntryint device, Byte index, Byte *pEntry Int seSetLutEntryint device, Byte index, Byte *pEntry Int seSetLutint device, Byte *pLutInt seDrawTextint device, char *fmt Int sePutcharint ch Int seGetcharvoidInt sePutcint device, int ch Int seSetPixelint device, int x, int y, Dword color Miscellaneous Int seDelayint device, Dword SecondsInt seSetRegint device, int index, Byte val Word seRotateByteRightBYTE val, Byte bits Word seRotateByteLeftBYTE val, Byte bitsSample Code Sample code using 13504HAL APISample code without using 13504HAL API Vancouver Design Center Pclk To arrive at the frame rate closest to the desired Words Fifo Supported Panel Values Appendix a Supported Panel ValuesPassive Single Panel Passive Dual PanelTFT 16-Bit Register Single TFT Panel01/02/02 Number of Bits/Pixel Document Number X19A-B-001-04 13504CFG.EXE Configuration ProgramVancouver Design Center X19A-B-001-04 13504CFG.EXE Program Requirements Script Mode Interactive ModeThis page Left Blank 13504CFG View Menu This page Left Blank 13504CFG.EXE Program Requirements InstallationUsage Script Mode 13504CFG Menu Bar Interactive ModeMaking 13504CFG Menu Selections Files Menu View Menu 13504CFG Current Configuration Device Menu Panel Edit Panel Setup CRT Edit CRT Setup Advanced Memory Edit Advanced Memory Setup Power Management Edit Power Setup Lookup Table LUT Edit LUT Setup Setup Help Menu Sample Program Messages CommentsThis page Left Blank Document Number X19A-B-002-05 13504SHOW Demonstration ProgramThis page Left Blank S1D13504 Supported Evaluation Platforms 13504SHOWProgram Messages Error Too many devices registeredDocument Number X19A-B-003-05 13504SPLT Display UtilityThis page Left Blank 13504SPLT 13504SPLT Example Comments This page Left Blank Document Number X19A-B-004-05 13504VIRT Display UtilityS1D13504 13504VIRT Display Utility X19A-B-004-05 13504VIRT 13504VIRT Example Comments This page Left Blank Document Number X19A-B-005-05 13504PLAY Diagnostic UtilityThis page Left Blank 13504PLAY Reads/writes the registers Scripting 13504PLAY ExampleComments Document Number X19A-B-006-04 13504BMP Demonstration ProgramThis page Left Blank 13504BMP Program Messages Document Number X19A-B-007-04 13504PWR Software Suspend Power Sequencing UtilityX19A-B-007-04 Issue Date 01/02/01 13504PWR Selects software suspend Error Unknown command line argument This page Left Blank Document Number X19A-B-008-02 13504DCFG Configuration ProgramThis page Left Blank Table of Contents This page Left Blank Clocks Tab Panel Tab List of FiguresThis page Left Blank 13504DCFG InstallationUsage 13504DCFG Configuration Tabs General Tab General TabMemory Tab Memory TabClocks Tab Clocks TabClki Clocks TabLCD Mclkpclk CRT MclkpclkPanel Tab Panel TabSTN/TFT Panel TabHRTC/FPLINE VRTC/FPFRAMECRT Tab CRT TabDefaults Tab Defaults TabSelect the default display device. Three display modes LCD Initializes the registers based on the default modeRegisters Tab Registers TabMiscellaneous Flags Tab Miscellaneous Flags TabSaving to a File Comments Resolution Frame Rate Hz Pclk MHz Supported Dram TypesDocument Number X19A-E-001-04 Windows CE Display DriversX19A-E-001-04 Program Requirements DIP SwitchExample Driver Builds Windows VersionWith this line Build For Cepc If CEPCDDIVGA2BPP Epson Research and Development Installation for Hitachi D9000 and Etma ODO Example InstallationInstallation for Cepc Environment Comments This page Left Blank Document Number X19A-E-002-03 Wind River WindML v2.0 Display DriversX19A-E-002-03 Issue Date 01/04/06 Wind River WindML v2.0 Display Drivers Make CPU=PENTIUM ugl Building a WindML v2.0 Display DriverEpson Research and Development This page Left Blank Document Number X19A-E-003-02 Wind River UGL v1.2 Display DriversX19A-E-003-02 Wind River UGL v1.2 Display Drivers Building a UGL v1.2 Display Driver Epson Research and Development This page Left Blank Document Number X19A-G-004-06 S1D13504 X19A-G-004-06 Issue Date 01/02/02 Parts List Schematic Diagrams Installation and ConfigurationThis page Left Blank S1D13504B00C Schematic Diagram 1 of 6 This page Left Blank Features Configuration DIP Switch Settings Installation and ConfigurationJumper Settings Host Bus SelectionLCD / Ramdac Interface Pin Mapping LCD Signal Connector J6CPU/BUS Connector H1 Pinout CPU / BUS Interface Connector PinoutsConnector Comments Pin No CPU/BUS Connector H2 Pinout DB150 D150 D3116 WE1# Host Bus Interface Pin MappingISA Bus Support Technical DescriptionDram Support Non-ISA Bus SupportDecode Logic Clock Input SupportColor Passive LCD Panel Support Monochrome LCD Panel SupportColor TFT LCD Panel Support External Cmos Ramdac SupportCore VDD Power Supply Power Save ModesIO VDD Power Supply Adjustable LCD Panel Negative Power Supply15 CPU/Bus Interface Header Strips Schematic NotesItem # Qty/board Designation Part Value Description Parts ListTexas Instrument PAL 24 pin DIP package/socketed TIBPAL22V10-15BCNTDiagrams SchematicS1D13504B00C Schematic Diagram 2 Rev.1.0 S1D13504B00C Schematic Diagram 4 Diagram 5 S1D13504B00C Schematic Diagram 6 This page Left Blank Document Number X19A-G-003-05 S5U13504-D9000S5U13504-D9000 X19A-G-003-05 Issue Date 01/02/02 D9000 Specifics Introduction FeaturesThis page Left Blank S5U13504-D9000 Perspective View This page Left Blank Reference Display Buffer S1D13504 Color Graphics LCD ControllerLCD Display Support LCD Interface Pin Mapping LCD Connector PinoutCRT Support Adjustable LCD Bias Power SupplyConnector Pinout for Channel A6 and A7 Interface SignalsInterface Signals D9000 SpecificsGND Connector Pinout for Channel A7DC12V Channel A7 Pin # Fpga Signal S1D13504 Signal SmZ Channel A6 Pin # Fpga Signal S1D13504 Signal SmXY Connectors Pinout for Channel A6BS# GND Channel A6 Pin # Fpga Signal S1D13504 Signal SmZ Bus Interface Timing Board DimensionsMemory Address CS#, M/R# Decode Makefpga fileItem # Qty Reference Part Description Parts ListSchematic S5U13504-D9000 Schematic Diagram 2 S5U13504-D9000 Schematic Diagram 3 D9000 Component Placement PCB Layout Component PlacementS5U13504-D9000 Perspective View Perspective ViewDocument Number X19A-G-006-04 Power ConsumptionS1D13504 Power Consumption X19A-G-006-04 S1D13504 Power Consumption Summary S1D13504 Total Power ConsumptionConditions Document Number X19A-G-005-08 Interfacing to the Philips Mips PR31500/PR31700 ProcessorThis page Left Blank Direct Connection to the Philips PR31500/PR31700 This page Left Blank List of Tables S1D13504 to PR31500/PR31700 Connection using One IT8368EThis page Left Blank Introduction Interfacing to the PR31500/PR31700 S1D13504 Host Bus Interface WAIT# RESET#Generic MPU Host Bus Interface Pin Mapping S1D13504 Generic MPU Pin NamesGeneric MPU Host Bus Interface Signals Hardware Description Direct Connection to the Philips PR31500/PR31700Memory Mapping and Aliasing MD1 MD2 S1D13504 ConfigurationMD3 MD4 Hardware Description-Using One IT8368E System Design Using the IT8368E PC Card BufferLogic Chip SelectVancouver Design Center PR31500/PR31700 S1D13504 Hardware Description-Using Two IT8368E’sIT8368E Configuration IT8368E Uses PC Card Slot # Philips Address Size Function TX3912 Address Size Function CARDnIOEN=0 CARDnIOEN=1S1D13504 Configuration using the IT8368E Software Documents ReferencesDocument Sources Epson LCD/CRT Controllers S1D13504 Technical SupportPhilips Mips PR31500/PR31700 Processor ITE IT8368EThis page Left Blank Document Number X19A-G-007-07 Interfacing to the NEC VR4102 MicroprocessorX19A-G-007-07 Issue Date 01/02/02 Introduction Interfacing to the NEC VR4102 This page Left Blank NEC VR4102 Read/Write Cycles This page Left Blank Introduction NEC VR4102 System Bus Interfacing to the NEC VR4102Overview Lcdrdy LCD Memory Access CyclesS1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Read/Write VR4102 to S1D13504 InterfaceDecode Logic Generic bus interface e.g. MPC821, ISA bus interface S1D13504 Hardware ConfigurationNEC Signals Cycle S1D13504 Signals NEC VR4102 ConfigurationWR# WriteSoftware References Japan North America Taiwan, R.O.C NEC Electronics Inc. VR4102This page Left Blank Interfacing to the Motorola MCF5307 Coldfire Microprocessor X19A-G-011-07 Issue Date 01/02/02 S1D13504 Bus Interface This page Left Blank List of Tables This page Left Blank Introduction MCF5307 System Bus Interfacing to the MCF5307Normal Non-Burst Bus Transactions MCF5307 Memory Read Cycle Burst Cycles Chip-Select ModuleS1D13504 Bus Interface Generic MPU Host Bus Interface Signals Hardware Connections MCF5307 To S1D13504 InterfaceS1D13504 Configuration Settings Memory/Register Mapping MCF5307 Chip Select ConfigurationSoftware Motorola Inc. Motorola Literature Distribution Center, 800 Motorola MCF5307 Processor S1D13504 Color Graphics LCD / CRT Controller X19A-G-013-02 Issue Date 01/02/02 Introduction Interfacing to the MC68328 This page Left Blank Generic MPU Host Bus Interface Pin Mapping This page Left Blank Introduction 68328 System Bus Interfacing to the MC68328S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals MC68328 To S1D13504 Interface Busclk RESET#CSB3 Dtack UWE LWE CLK0 MD7 MD6Option Memory Selection MC68328 Chip Select ConfigurationSoftware References Motorola MC68328 Processor This page Left Blank Interfacing to the Motorola MPC821 Microprocessor X19A-G-010-05 Issue Date 01/02/02 Introduction Interfacing to the MPC821 This page Left Blank List of Tables This page Left Blank Introduction MPC8xx System Bus Interfacing to the MPC821MPC821 Bus Overview Power PC Memory Read Cycle Power PC Memory Write Cycle General-Purpose Chip Select Module Gpcm Memory Controller ModuleUser-Programmable Machine UPM S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Typical Implementation of MPC821 to S1D13504 Interface MPC821 to S1D13504 InterfaceAB8 AB9AB7 AB6Sysclk SresetCS4 WE0S1D13504 Hardware Configuration Register/Memory Mapping MPC821 Chip Select ConfigurationSource Code Test SoftwareEpson Research and Development Software References Motorola MPC821 Processor Document Number X19A-G-009-05 Interfacing to the PC Card BusThis page Left Blank Introduction Interfacing to the PC Card Bus This page Left Blank PC Card Read Cycle This page Left Blank Introduction Interfacing to the PC Card Bus Memory Access CyclesPC Card System Bus PC Card OverviewPC Card Read Cycle S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Typical Implementation of PC Card to S1D13504 Interface PC Card to S1D13504 InterfaceGeneric MPU SH-3Equations PAL EquationsSoftware PCMCIA/JEIDA, PC Card Standard -- March Pcmcia PC Card StandardThis page Left Blank Document Number X19A-G-012-04 Interfacing to the Toshiba Mips TX3912 ProcessorThis page Left Blank Direct Connection to the Toshiba TX3912 This page Left Blank S1D13504 to TX3912 Connection using One IT8368E This page Left Blank Introduction Interfacing to the TX3912 S1D13504 Host Bus Interface Generic MPU Host Bus Interface Signals Direct Connection to the Toshiba TX3912 Memory Mapping and Aliasing S1D13504 Hardware Configuration System Design Using the IT8368E PC Card Buffer S1D13504 to TX3912 Connection using One IT8368E Hardware Description-Using Two IT8368E’s S1D13504 to TX3912 Connection using Two IT8368E IT8368E Configuration 64Mb Card 2 Attribute 64Mb64Mb Card 1 Memory 64Mb Card 2 MemoryS1D13504 Configuration Software References Toshiba Mips TX3912 Processor ITE IT8368E This page Left Blank