Epson S1D13504 manual Memory Controller Module, General-Purpose Chip Select Module Gpcm

Epson Research and Development	Page 11
Vancouver Design Center

Burst cycles are mainly intended to facilitate cache line fills from program or data memory. They are normally not used for transfers to/from IO peripheral devices such as the S1D13504, therefore the interfaces described in this document do not attempt to support burst cycles. However, the example interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the S1D13504 address space.

2.3 Memory Controller Module

2.3.1 General-Purpose Chip Select Module (GPCM)

The General-Purpose Chip Select Module (GPCM) is used to control memory and peripheral devices which do not require special timing or address multiplexing. In addition to the chip select output, it can generate active-low Output Enable (OE) and Write Enable (WE) signals compatible with most memory and x86-style peripherals. The MPC821 bus controller also provides a Read/Write (RD/WR) signal which is compatible with most 68K peripherals.

The GPCM is controlled by the values programmed into the Base Register (BR) and Option Register (OR) of the respective chip select. The Option Register sets the base address, the block size of the chip select, and controls the following timing parameters:

•The ACS bit field allows the chip select assertion to be delayed with respect to the address bus valid, by 0, ¼ , or ½ clock cycle.

•The CSNT bit causes chip select and WE to be negated ½ clock cycle earlier than normal.

•The TRLX (relaxed timing) bit will insert an additional one clock delay between asser- tion of the address bus and chip select. This accommodates memory and peripherals with long setup times.

•The EHTR (Extended hold time) bit will insert an additional 1-clock delay on the first access to a chip select.

•Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself by asserting TA (Transfer Acknowledge).

•Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its memory space is addressed by the processor core.

Interfacing to the Motorola MPC821 Microprocessor	S1D13504
Issue Date: 01/02/02	X19A-G-010-05