Epson S1D13504 5.4.2 Memory Interface

Epson Research and Development Page 25
Vancouver Design Center
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
5.4.2 Memory Interface
Table 5-2: Memory Interface Pin Descriptions
Pin Name Type
Pin #
Driver Reset = 0
Value Description
F00A
F01A F02A
LCAS#O5056CO1Output 1
This pin has multiple functions.
• For dual CAS# DRAM, this is the column address strobe for
the lower byte (LCAS#).
• For single CAS# DRAM, this is the column address strobe
(CAS#).
See Table 5-10: “Memory Interface Pin Mapping,” on page 32
for summary.
UCAS#O4955CO1Output 1
This pin has multiple functions.
• For dual CAS# DRAM, this is the column address strobe for
the upper byte (UCAS#).
• For single CAS# DRAM, this is the write enable signal for the
upper byte (UWE#).
See Table 5-10: “Memory Interface Pin Mapping,” on page 32
for summary.
WE# O 48 54 CO1 Output 1
This pin has multiple functions.
• For dual CAS# DRAM, this is the write enable signal (WE#).
• For single CAS# DRAM, this is the write enable signal for the
lower byte (LWE#).
See Table 5-10: “Memory Interface Pin Mapping,” on page 32
for summary.
RAS# O 47 53 CO1 Output 1 Row address strobe.
MD[15:0] IO
67, 65,
63, 61,
59, 57,
55, 53,
52, 54,
56, 58,
60, 62,
64, 66
76, 70,
68, 66,
64, 62,
60, 58,
59, 61,
63, 65,
67, 69,
75, 77
CD2/TS1 Hi-Z
(pulled 0)
These pins have multiple functions.
• Bi-directional memory data bus.
• During reset, these pins are inputs and their states at the
rising edge of RESET# are used to configure the chip.
Internal pull-down resistors (typical values of
100KΩ/100KΩ/120KΩ at 5.0V/3.3V/3.0V respectively) pull
the reset states to 0. External pull-up resistors can be used
to pull the reset states to 1. See Section 5.5,
“Summary of
Configuration Options”
on page 31.