Epson S1D13504 manual LCAS# CO1, UCAS# CO1, WE# CO1, RAS# CO1, CD2/TS1

Epson Research and Development	Page 25
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5.4.2 Memory Interface

Table 5-2: Memory Interface Pin Descriptions

		Pin #			Reset = 0
Pin Name	Type			Driver		Description
		F00A
			F02A		Value
		F01A
						This pin has multiple functions.
						• For dual CAS# DRAM, this is the column address strobe for
						the lower byte (LCAS#).
LCAS#	O	50	56	CO1	Output 1	• For single CAS# DRAM, this is the column address strobe
						(CAS#).
						See Table 5-10: “Memory Interface Pin Mapping,” on page 32
						for summary.
						This pin has multiple functions.
						• For dual CAS# DRAM, this is the column address strobe for
						the upper byte (UCAS#).
UCAS#	O	49	55	CO1	Output 1	• For single CAS# DRAM, this is the write enable signal for the
						upper byte (UWE#).
						See Table 5-10: “Memory Interface Pin Mapping,” on page 32
						for summary.
						This pin has multiple functions.
						• For dual CAS# DRAM, this is the write enable signal (WE#).
WE#	O	48	54	CO1	Output 1	• For single CAS# DRAM, this is the write enable signal for the
						lower byte (LWE#).
						See Table 5-10: “Memory Interface Pin Mapping,” on page 32
						for summary.
RAS#	O	47	53	CO1	Output 1	Row address strobe.
		67, 65,	76, 70,			These pins have multiple functions.
						• Bi-directional memory data bus.
		63, 61,	68, 66,
		59, 57,	64, 62,			• During reset, these pins are inputs and their states at the
MD[15:0]	IO	55, 53,	60, 58,	CD2/TS1	Hi-Z	rising edge of RESET# are used to configure the chip.
		52, 54,	59, 61,		(pulled 0)	Internal pull-down resistors (typical values of
		56, 58,	63, 65,			100KΩ/ 100KΩ/ 120KΩ at 5.0V/3.3V/3.0V respectively) pull
						the reset states to 0. External pull-up resistors can be used
		60, 62,	67, 69,
						to pull the reset states to 1. See Section 5.5, “Summary of
		64, 66	75, 77
						Configuration Options” on page 31.

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18