Epson Research and Development

Page 9

Vancouver Design Center

 

 

 

The following figure illustrates a typical memory read cycle on the MCF5307 system bus.

BCLK0

TS

TA

TIP

A[31:0]

R/W

SIZ[1:0], TT[1:0]

 

 

 

 

 

 

 

D[31:0]

 

 

 

Sampled when TA low

Transfer Start

Wait States

Transfer

Next Transfer

 

 

 

Complete

Starts

Figure 2-1: MCF5307 Memory Read Cycle

The following figure illustrates a typical memory read cycle on the MCF5307 system bus.

BCLK0

TS

TA

TIP

A[31:0]

R/W

SIZ[1:0], TT[1:0]

D[31:0] Valid

Transfer Start

Wait States

Transfer

Next Transfer

Complete Starts

Figure 2-2: MCF5307 Memory Write Cycle

Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor

S1D13504

Issue Date: 01/02/02

X19A-G-011-07

Page 411
Image 411
Epson S1D13504 manual MCF5307 Memory Read Cycle