Epson Research and Development

Page 83

Vancouver Design Center

 

 

 

7.4.12 16-Bit TFT Panel Timing

VNDP

VDP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FPFRAME

FPLINE

R[5:1], G[5:0], B[5:1] LINE480

DRDY

FPLINE

HNDP1

FPSHIFT

DRDY

R[5:1]

G[5:0]

B[5:1]

LINE1 LINE480

HDPHNDP2

1-1 1-2 1-640

1-1 1-2 1-640

1-1 1-2 1-640

Note: DRDY is used to indicate the first pixel

Example Timing for 640x480 panel

 

 

Figure 7-37: 16-Bit TFT Panel Timing

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

VNDP

= Vertical Non-Display Period

= (REG[0Ah] bits [5:0]) + 1

HDP

= Horizontal Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

HNDP

= Horizontal Non-Display Period

= HNDP1 + HNDP2 = ((REG[05h] bits [4:0]) + 1)*8Ts

Hardware Functional Specification

S1D13504

Issue Date: 01/01/30

X19A-A-002-18

Page 89
Image 89
Epson S1D13504 manual 12 16-Bit TFT Panel Timing, = Vertical Display Period = REG09h bits 10, REG08h bits 70 +