Epson S1D13504 manual Suspend Disable Sequence, LCD Enable/Disable Sequencing Reg0D bit

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3.Enable Hardware Suspend: this same 128 frame delay still applies however the actual frame period is now greatly reduced.

4.Disable Hardware Suspend.

5.Restore the Horzontal and Vertical resolution registers to their original values.

6.Enable the Display FIFO.

5.4.2Suspend Disable Sequence

Disable Suspend (either {REG[1A] bit 0 = 0, or SUSPEND# pin inactive): LCDPWR# and FPFRAME will start within 1 frame, while the remaining LCD interface signals will start immedi- ately.

5.5 LCD Enable/Disable Sequencing (Reg[0D] bit 0)

In an LCD only product, the LCD Enable bit should only be disabled automatically by using a Power Save Mode. In a product having both a CRT and LCD, this bit will need to be controlled manually - examples for both situations are given below.

LCD Enable / Disable using Power Save Modes

In all supported Power Save Modes, the LCD Enable bit and associated functionality is automati- cally controlled by the internal Power Save circuitry. See above for Power Save sequences.

LCD Enable / Disable using Manual Control

It may become necessary to enable / disable the LCD when switching back and forth to and from the CRT. In this case care must be taken when disabling the LCD with respect to the external Power Supply used to provide the LCD Drive voltage. The LCD Drive voltage must be 0V before removing the LCD interface signals to prevent panel damage.

Enable

Setting REG[0D] bit 0=1: immediately enables the LCD interface signals. Note: FPLINE, FPSHIFT2/DRY signals are always toggling regardless of the state of this bit and are only shut- down completely during Power Save Modes. The LCDPWR# pin will go to its active state immedi- ately after the LCD Enable bit is set.

Disable

Setting REG[0D] bit 0=0: LCDPWR# will go to its inactive state within one vertical frame, while maintaining the LCD interface signals for 128 Vertical Frames (with the exception of FPFRAME which goes inactive at the same time as LCDPWR#).

If 128 frames is not enough 'time' to allow the LCD Drive power supply to decay to 0V, LCDPWR# can be controlled manually using REG[1A] bit 3.

S1D13504	Programming Notes and Examples
X19A-G-002-07	Issue Date: 01/02/01