Epson manual S1D13504 Configuration

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	Vancouver Design Center

5.5 S1D13504 Configuration

The S1D13504 latches MD0 through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13504 Hardware Specification, document number X19A-A-002-xx.

The partial table below only shows those configuration settings relevant to the IT8368E implementation.

Table 5-3: S1D13504 Configuration using the IT8368E

S1D13504	value on this pin at rising edge of RESET# is used to configure:(1/0)
Pin Name
	1	0
MD0	8-bit host bus interface	16-bit host bus interface
MD1
MD2	See “Host Bus Selection” table below	See “Host Bus Selection” table below
MD3
MD4	Little Endian	Big Endian
MD5	WAIT# signal is active high	WAIT# signal is active low
	= required configuration for connection using ITE IT8368E

Table 5-4: S1D13504 Host Bus Selection using the IT8368E

MD3	MD2	MD1	Host Bus Interface
0	0	0	SH-3 bus interface
0	0	1	MC68K bus 1 interface (e.g. MC68000)
0	1	0	MC68K bus 2 interface (e.g. MC68030)
0	1	1	Generic bus interface (e.g. MCF5307, ISA bus interface)
1	x	x	Reserved
	= required configuration for connection using ITE IT8368E

S1D13504	Interfacing to the Toshiba MIPS TX3912 Processor
X19A-G-012-04	Issue Date: 01/02/02