Epson S1D13504 manual D3116 hold from falling edge of DSACK1# write cycle

Epson Research and Development	Page 41
Vancouver Design Center

Table 7-3: MC68K Bus 2 Interface Timing

Symbol	Parameter	Min	Max	Units
t1	Clock period	30		ns
t2	Clock pulse width high	5		ns
t3	Clock pulse width low	5		ns
t4	A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0 AS# =	4		ns
	0, and either UDS#=0 or LDS# = 0
t5	A[20:0], SIZ[1:0], M/R# hold from AS#	0		ns
t6	CS# hold from AS#	0		ns
t7	R/W# setup to DS#	5		ns
t8	R/W# hold from AS#	0		ns
t91	AS# = 0 and CS# = 0 to DSACK1# driven high	1		ns
t10	AS# high to DSACK1# high impedance	1	5	ns
t11	D[31:16] valid to second CLK where CS# = 0 AS# = 0, and	0		ns
	either UDS#=0 or LDS# = 0 (write cycle)
t12	D[31:16] hold from falling edge of DSACK1# (write cycle)	0		ns
t132	Falling edge of UDS# = 0 or LDS# = 0 to D[31:16] driven (read	3		ns
	cycle)
t14	D[31:16] valid to DSACK1# falling edge (read cycle)	0		ns
t15	UDS# and LDS# high to D[31:16] invalid/high impedance (read	2	11	ns
	cycle)
t16	AS# high setup to CLK	3		ns

1.If the S1D13504 host interface is disabled, the timing for DSACK1# driven high is relative to the falling edge of AS# or the first positive edge of CLK after A[20:0] and M/R# become valid, whichever occurs later.

2.If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# becomes valid, whichever occurs later.

Hardware Functional Specification	S1D13504
Issue Date: 01/01/30	X19A-A-002-18