Epson Research and Development Page 5
Vancouver Design Center
Interfacing to the Toshiba MIPS TX3912 Processor S1D13504
Issue Date: 01/02/02 X19A-G-012-04
List of Tables
Table 3-1: Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4-1: S1D13504 Configuration for Direct Connection. . . . . . . . . . . . . . . . . . . . . . 13
Table 4-2: S1D13504 Host Bus Selection for Direct Connection . . . . . . . . . . . . . . . . . . . 13
Table 5-1: TX3912 to Unbuffered PC Card Slots System Address Mapping . . . . . . . . . . . . . 19
Table 5-2: TX3912 to PC Card Slots Address Remapping using the IT8368E . . . . . . . . . . . . 19
Table 5-3: S1D13504 Configuration using the IT8368E . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5-4: S1D13504 Host Bus Selection using the IT8368E. . . . . . . . . . . . . . . . . . . . . 20
List of Figures
Figure 4-1: Typical Implementation of TX3912 to S1D13504 Direct Connection. . . . . . . . . . . 11
Figure 5-1: S1D13504 to TX3912 Connection using One IT8368E . . . . . . . . . . . . . . . . . .15
Figure 5-2: S1D13504 to TX3912 Connection using Two IT8368E . . . . . . . . . . . . . . . . . . 17