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GRAPHICS S1D13504
S1D13504 COLOR GRAPHICS LCD/CRT CONTROLLER
X19A-C-002-11 2
GRAPHICS S1D13504
CPU
S1D13504
RAMDAC
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1.1 Scope
1.2 Overview Description
2 Features
2.1 Memory Interface
2.2 CPU Interface
2.3 Display Support
2.4 Display Modes
2.5 Clock Source
2.6 Miscellaneous
2.7 Package and Pin
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3 Typical System Implementation Diagrams
Figure 3-1: Typical System Diagram SH-3 Bus, 1Mx16 FPM/EDO-DRAM
SH-3
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Figure 3-2: Typical System Diagram MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
256Kx16
Figure 3-3: Typical System Diagram MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
MC68000
MC68030
Figure 3-4: Typical System Diagram Generic Bus, 1Mx16 FPM/EDO-DRAM
GENERIC
4 Block Description
4.1 Functional Block Diagram
Figure 4-1: System Block Diagram Showing Datapaths
4.2 Functional Block Descriptions 4.2.1 Host Interface
4.2.2 Memory Controller
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5 Pin Out
5.1 Pinout Diagram for S1D13504F00A
Figure 5-1: Pinout Diagram of F00A Package type: 128 pin surface mount QFP15
S1D13504F00A
5.2 Pinout Diagram for S1D13504F01A
Figure 5-2: Pinout Diagram of F01A Package type: 128 pin surface mount TQFP15
S1D13504F01A
5.3 Pinout Diagram for S1D13504F02A
Figure 5-3: Pinout Diagram of F02A Package type: 144 pin surface mount QFP20
S1D13504F02A
1 2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 2223 24 25 26 27 28 29 30 31 32 33 34 3536
5.4 Pin Description
Key:
5.4.1 Host Interface
Register Mapping
.
Summary of Configuration Options
5.4.2 Memory Interface
Summary of Configuration Options
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5.4.3 LCD Interface
5.4.4 Clock Input
Summary of Configuration Options
Power Save Modes
5.4.5 CRT and External RAMDAC Interface
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5.4.6 Miscellaneous
5.4.7 Power Supply
Power Save Modes
5.5 Summary of Configuration Options
5.6 Multiple Function Pin Mapping
Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping
6 D.C. Characteristics
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7 A.C. Characteristics
7.1 CPU Interface Timing 7.1.1 SH-3 Interface Timing
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7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000)
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7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030)
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7.1.4 Generic MPU Interface Synchronous Timing
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7.1.5 Generic MPU Interface Asynchronous Timing
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7.2 Clock Input Requirements
7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read Timing
Figure 7-7: EDO-DRAM Read Timing
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7.3.2 EDO-DRAM Write Timing
Figure 7-8: EDO-DRAM Write Timing
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7.3.3 EDO-DRAM Read-Write Timing
Figure 7-9: EDO-DRAM Read-Write Timing
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7.3.4 EDO-DRAM CAS Before RAS Refresh Timing
7.3.5 EDO-DRAM Self-Refresh Timing
7.3.6 FPM-DRAM Read Timing
Figure 7-12: FPM-DRAM Read Timing
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7.3.7 FPM-DRAM Write Timing
Figure 7-13: FPM-DRAM Write Timing
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7.3.8 FPM-DRAM Read-Write Timing
Figure 7-14: FPM-DRAM Read-Write Timing
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7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing
7.3.10 FPM-DRAM Self-Refresh Timing
7.4 Display Interface 7.4.1 Power-On/Reset Timing
Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock.
7.4.2 Su spend Timing
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7.4.3 Single Monochrome 4-Bit Panel Timing
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7.4.4 Single Monochrome 8-Bit Panel Timing
Figure 7-21: Single Monochrome 8-Bit Panel Timing
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7.4.5 Single Color 4-Bit Panel Timing
Figure 7-23: Single Color 4-Bit Panel Timing
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7.4.6 Single Color 8-Bit Panel Timing (Format 1)
Figure 7-25: Single Color 8-Bit Panel Timing (Format 1)
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7.4.7 Single Color 8-Bit Panel Timing (Format 2)
Figure 7-27: Single Color 8-Bit Panel Timing (Format 2)
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7.4.8 Single Color 16-Bit Panel Timing
Figure 7-29: Single Color 16-Bit Panel Timing
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7.4.9 Dual Monochrome 8-Bit Panel Timing
Figure 7-31: Dual Monochrome 8-Bit Panel Timing
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7.4.10 Dual Color 8-Bit Panel Timing
Figure 7-33: Dual Color 8-Bit Panel Timing
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7.4.11 Dual Color 16-Bit Panel Timing
Figure 7-35: Dual Color 16-Bit Panel Timing
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7.4.12 16-Bit TFT Panel Timing
Figure 7-37: 16-Bit TFT Panel Timing
Figure 7-38: TFT A.C. Timing
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7.4.13 CRT Timing
Figure 7-39: CRT Timing
Figure 7-40: CRT A.C. Timing
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7.4.14 External RAMDAC Read / Write Timing
Write
Read
8 Registers
8.1 Register Mapping
8.2 Register Descriptions
8.2.1 Revision Code Register
8.2.2 Memory Configuration Registers
8.2.3 Panel/Monitor Configuration Registers
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8.2.4 Display Configuration Registers
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8.2.5 Clock Configuration Register
8.2.6 Power Save Configuration Registers
8.2.7 Miscellaneous Registers
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8.2.8 Look-Up Table Registers
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8.2.9 External RAMDAC Control Registers
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9 Display Buffer
The display buffer will contain an image buffer and may also contain a half-frame buffer.
9.1 Image Buffer
9.2 Half Frame Buffer
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10 Display Configuration
10.1 Display Mode Data Format
Figure 10-1: 1/2/4/8 Bit-Per-Pixel Format Memory Organization
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Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization
10.2 Image Manipulation
11 Clocking
11.1 Maximum MCLK: PCLK Ratios
11.2 Frame Rate Calculation
The frame rate is calculated using the following formula:
Where:
50ns
60ns
12 Look-Up Table Architecture
12.1 Gray Shade Display Modes
1 Bit-Per-Pixel Mode
2 Bit-Per-Pixel Mode
Figure 12-2: 2 Bit-Per-Pixel 4-Level Gray-Shade Mode Look-Up Table Architecture
4 Bit-Per-Pixel Mode
Figure 12-3: 4 Bit-Per-Pixel 16-Level Gray-Shade Mode Look-Up Table Architecture
12.2 Color Display Modes
1 Bit-Per-Pixel Color Mode
Figure 12-4: 1 Bit-Per-Pixel 2-Level Color Look-Up Table Architecture
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2 Bit-Per-Pixel Color Mode
Figure 12-5: 2 Bit-Per-Pixel 4-Level Color Mode Look-Up Table Architecture
Red Look-Up Table
Green Look-Up Table
Blue Look-Up Table
4 Bit-Per-Pixel Color Mode
Figure 12-6: 4 Bit-Per-Pixel 16-Level Color Mode Look-Up Table Architecture
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8 Bit-Per-Pixel Color Mode
Figure 12-7: 8 Bit-Per-Pixel 256-Level Color Mode Look-Up Table Architec ture
76543210 R2 R1 R0 G2 G1 G0 B1 B0
256 Color Data Format: Red Look-Up Table
Green Look-Up Table
13 Power Save Modes
13.1 Hardware Suspend
13.2 Software Suspend
13.3 Power Save Mode Function Summary
13.4 Pin States in Power Save Modes
14 Mechanical Data
14.1 QFP15-128 (S1D13504F00A)
Figure 14-1: Mechanical Drawing QFP15-128
QFP15 - 128 pin
Unit: mm
14.2 TQFP15-128 (S1D13504F01A)
TQFP15 - 128 pin Unit: mm
1.2
0.1
1
14.3 QFP20-144 (S1D13504F02A)
QFP20 - 144 pin Unit: mm
1.7
0.1
1.4
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2 Programming the S1D13504 Registers
2.1 Registers Requiring Special Consideration 2.1.1 REG[01] bit 0 - Memory Type
2.1.2 REG[22] bits 7-2 - Performance Enhancement Register 0
2.1.3 REG[02] bit 1 - Dual/Single Panel Type
2.1.4 REG[1B] bit 0 - Half Frame Buffer Disable
2.1.5 REG[23] Display FIFO:
2.2 Register Initialization 2.2.1 Initialization Sequence
2.2.2 Initialization Example
2.2.3 Re-Programming Registers
2.3 Disabling the Half Frame Buffer Sequence:
3 Display Buffer
3.1 Display Buffer Location
3.2.2 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades)
3.2.3 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades)
3.2.4 Memory Organization for Eight Bit-per-pixel (256 Colors)
3.2.5 Memory Organization for 15 Bit-per-pixel (32768 Colors)
3.2.6 Memory Organization for 16 Bit-per-pixel (65536 Colors)
3.3 Look-Up Table (LUT)
3.3.1 Look-Up Table Registers
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3.3.2 Look-Up Table Organization
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4 Advanced Techniques
4.1 Virtual Display
4.1.1 Registers
4.1.2 Examples
4.2 Panning and Scrolling
4.2.1 Registers
Table 4-1: Number of Pixels Panned Using Start Address
Table 4-2: Active Pixel Pan Bits
4.2.2 Examples
4.3 Split Screen
4.3.1 Registers
4.3.2 Examples
5 LCD Power Sequencing and Power Save Modes
5.1 Introduction to LCD Power Sequencing
5.2 Introduction to Power Save Modes
5.3 Registers
5.4 Suspend Sequencing
5.4.1 Suspend Enable Sequence
5.4.2 Suspend Disable Sequence
5.5 LCD Enable/Disable Sequencing (Reg[0D] bit 0)
6 CRT Considerations
6.1 Introduction
6.1.1 CRT Only
6.1.2 Simultaneous Display
Table 6-3: 8 bpp Recommended RAMDAC palette data for Simultaneous Display
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Table 6-4: Related register data for Simultaneous Display
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8 Hardware Abstraction Layer (HAL)
int seGetId(int device, BYTE *pId)
int seInitHal(void)
int seSetInit(int device)
int seValidRegisteredDevice(int device)
int seValidStdDevice(int device)
8.2.2 Screen Manipulation int seDisplayEnable(int device, BYTE NewState)
int seGetBitsPerPixel(int device, BYTE *pBitsPerPixel)
int seGetBytesPerScanline(int device, int *pBytes)
int seGetLastUsableByte(int device, DWORD *pLastByte)
int seGetLinearDispAddr(int device, DWORD *pDispLogicalAddr)
int seGetScreenSize(int device, int *width, int *height)
int seReadDisplayByte(int device, DWORD offset, BYTE *pByte)
int seReadDisplayWord(int device, DWORD offset, WORD *pWord)
int seReadDisplayDword(int device, DWORD offset, DWORD *pDword)
int seSetBitsPerPixel(int device, BYTE BitsPerPixel)
int seSplitInit(int device, DWORD Scrn1Addr, DWORD Scrn2Addr)
int seSplitScreen(int device, BYTE WhichScreen, int VisibleScanlines)
int seVirtInit(int device, int xVirt, long *yVirt)
int seVirtMove(int device, BYTE WhichScreen, int x, int y)
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8.2.3 Color Manipulation int seGetDac(int device, BYTE *pDac)
int seGetDacEntry(int device, BYTE index, BYTE *pEntry)
int seGetLut(int device, BYTE *pLut)
int seGetLutEntry(int device, BYTE index, BYTE *pEntry);
int seSetDac(int device, BYTE *pDac)
int seSetDacEntry(int device, BYTE index, BYTE *pEntry)
int seSetLut(int device, BYTE *pLut)
int seSetLutEntry(int device, BYTE index, BYTE *pEntry)
int seGet15BppInfo(int device, unsigned *RedMask, unsigned *GreenMask, unsigned *BlueMask)
8.2.4 Drawing int seDrawLine(int device, int x1, int y1, int x2, int y2, DWORD color)
int seDrawText(int device, char *fmt, ...)
int seFillRect(int device, int x1, int y1, int x2, int y2, DWORD color)
int seGetchar(void)
int sePutchar(int ch)
int sePutc(int device, int ch)
int seSetPixel(int device, int x, int y, DWORD color)
8.2.5 Register Manipulation int seGetReg(int device, int index, BYTE *pVal)
int seSetReg(int device, int index, BYTE val)
8.2.6 Miscellaneous int seDelay(int device, DWORD Seconds)
WORD seRotateByteLeft(BYTE val, BYTE bits)
WORD seRotateByteRight(BYTE val, BYTE bits)
9 Sample Code
9.1 Introduction
9.1.1 Sample code using 13504HAL API
9.1.2 Sample code without using 13504HAL API
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Appendix A Supported Panel Values
A.1 Supported Panel Values
Table 9-2: Passive Dual Panel
Table 9-3: TFT Panel
S1D13504F00A Register Summary X19A-Q-001-03
S1D13504F00A Register Summary
e 1 01/02/02
Pa g
S1D13504F00A Register Summary X19A-Q-001-03
e 2 01/02/02
Pa g
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13504CFG.EXE
Program Requirements
Script Mode
Interactive Mode
13504CFG Menu Bar
Viewing 13504CFG Menu Contents
Making 13504CFG Menu Selections
Files Menu
View Menu
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Device Menu
Panel
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CRT
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Advanced Memory
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Power Management
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Lookup Table (LUT)
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Setup
Help Menu
Sample Program Messages
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13504SHOW
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13504SPLT
13504SPLT Example
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13504VIRT
13504VIRT Example
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13504PLAY
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13504PLAY Example
Scripting
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13504BMP
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13504PWR
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S1D13504 Color Graphics LCD/CRT Controller
13504DCFG Configuration Program
Document Number: X19A-B-008-02
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13504DCFG
Installation
Usage
13504DCFG Configuration Tabs
General Tab
Memory Tab
Figure 2: Memory Tab The Memory Tab selects the following m emory related settings.
Clocks Tab
The Clocks Tab allows the user to select the following settings.
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The Panel Tab select the following panel settings.
S1D13504 Hardware Functional Specification
CRT Tab
Figure 5: CRT Tab The CRT Tab selects the following CRT settings.
S1D13504 Hardware Functional Specification
Defaults Tab
Registers Tab
Miscellaneous Flags Tab
Saving to a File
Comments
S1D13504 Color Graphics LCD/CRT Controller
Windows CE Display Drivers
Document Number: X19A-E-001-04
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WINDOWS CE DISPLAY DRIVERS
Program Requirements Example Driver Builds
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Example Installation
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Wind River WindML v2.0 Display Drivers
Building a WindML v2.0 Display Driver
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S1D13540 Color Graphics LCD/CRT Controller
Wind River UGL v1.2 Display Drivers
Document Number: X19A-E-003-02
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Wind River UGL v1.2 Display Drivers
Building a UGL v1.2 Display Driver
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1.1 Features
2 Installation and Configuration
3 LCD / RAMDAC Interface Pin Mapping
Table 3-1: LCD Signal Connector (J6)
4 CPU / BUS Interface Connector Pinouts
Table 4-1: CPU/BUS Connector (H1) Pinout
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5 Host Bus Interface Pin Mapping
6 Technical Description
6.1 ISA Bus Support
6.2 Non-ISA B us Support
6.3 DRAM Support
6.4 Decode Logic
6.5 Clock Input Support
6.6 Monochrome LCD Panel Support
6.7 Color Passive LCD Panel Support
6.8 Color TFT LCD Panel Support
6.9 External CMOS RAMDAC Support
6.10 Power Save Modes
6.11 Core VDD Power Supply
6.12 IO VDD Power Supply
6.13 Adjustable LCD Panel Negative Power Supply
6.14 Adjustable LCD Panel Positive Power Supply
6.15 CPU/Bus Interface Header Strips
6.16 Schematic Notes
7 Parts List
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8 Schematic Diagrams
Figure 1: S1D13504B00C Schematic Diagram (1 of 6)
Figure 2: S1D13504B00C Schematic Diagram (2 of 6)
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Figure 3: S1D13504B00C Schematic Diagram (3 of 6)
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Figure 4: S1D13504B00C Schematic Diagram (4 of 6)
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Figure 5: S1D13504B00C Schematic Diagram (5 of 6)
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Figure 6: S1D13504B00C Schematic Diagram (6 of 6)
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S5U13504-D9000
Evaluation Board User Manual
Document Number: X19A-G-003-05
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2 Features
2.1 S1D13504 Color Graphics LCD Controller
2.1.1 Display Buffer
2.1.2 LCD Display Support
2.1.3 LCD Interface Pin Mapping
Table 2-1: LCD Connector Pinout
2.1.4 CRT Support
2.1.5 Adjusta ble LCD BIAS Power Supply
3 D9000 Specifics
3.1 Interface Signals
3.1.1 Connector Pinout for Channel A6 and A7
Table 3-1: Interface Signals
Table 3-2: Connector Pinout for Channel A7
Table 3-2: Connector Pinout for Channel A7 (C ontinued)
Table 3-2: Connector Pinout for Channel A7 (Continued)
Table 3-3: Connectors Pinout for Channel A6
Table 3-3: Connectors Pinout for Channel A6 (Continued)
3.1.2 Bus Interface Timing
3.1.3 Memory Address (CS#, M/R#) Decode
3.1.4 Makefpga file
3.2 Board Dimensions
3.3 Support Documentation Notes
3.4 Parts List
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Evaluation Board User Manual S5U13504-D9000 Issue Date: 01/02/02 X19A-G-003-05
3.5 Schematic Diagrams
CC
Figure 3-1: S5U13504-D9000 Schematic Diagram (1 of 4)
S5U13504-D9000 Evaluation Board User Manual X19A-G-003-05 Issue Date: 01/02/02
CC
Figure 3-2: S5U13504-D9000 Schematic Diagram (2 of 4)
Evaluation Board User Manual S5U13504-D9000 Issue Date: 01/02/02 X19A-G-003-05
Figure 3-3: S5U13504-D9000 Schematic Diagram (3 of 4)
Page 22 Epson Research and Development
S5U13504-D9000 Evaluation Board User Manual X19A-G-003-05 Issue Date: 01/02/02
Figure 3-4: S5U13504-D9000 Schematic Diagram (4 of 4)
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3.5.3 Perspective View
Figure 3-6: S5U13504-D9000 Perspective View
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1 S1D13504 Power Consumption
1.1 Conditions
2 Summary
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List of Tables
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2 Interfacing to the PR31500/PR31700
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4 Direct Connection to the Philips PR31500/PR31700
Figure 4-1: Typical Implementation of S1D13504 to PR31500/PR31700 Direct Connection
4.2 Memory Mapping and Aliasing
4.3 S1D13504 Configuration
5 System Design Using the IT8368E PC Card Buffer
5.1 Hardware DescriptionUsing One IT8368E
Figure 5-1: S1D13504 to PR31500/PR31700 Connection using One IT8368E
IT8368E
, document number
S1D13504 Hardware Functional Specification
Latch
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5.2 Hardware DescriptionUsing Two IT8368Es
Figure 5-2: S1D13504 to PR31500/PR31700 Connection using Two IT8368E
PR31500/PR31700
5.3 IT8368E Configuration
5.4 Memory Mapping and Aliasing
5.5 S1D13504 Configuration
6 Software
7 References
7.1 Documents
7.2 Document Sources
8 Technical Support
8.1 EPSON LCD/CRT Controllers (S1D13504)
8.3 ITE IT8368E
8.2 Philips MIPS PR31500/PR31700 Processor
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2 Interfacing to the NEC VR4102
2.1 The NEC VR4102 System Bus
2.1.1 Overview
2.1.2 LCD Memory Access Cycles
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4 VR4102 to S1D13504 Interface
Notes: The propagation delay of the Read/write Decode Logic show n above must be less than 10 nsec.
Figure 4-1: Typical Implementation of VR4102 to S1D13504 Interface
Read/Write Decode Logic
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4.3 NEC VR4102 Configuration
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7.2 NEC Electronics Inc. (VR4102).
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2 Interfacing to the MCF5307
2.1 The MCF5307 System Bus
2.1.1 Overview
2.1.2 Normal (Non-Burst) Bus Transactions
The following figure illustrates a typical memory read cycle on the MCF5307 system bus.
Figure 2-2: MCF5307 Memory Write Cycle
2.1.3 Burst Cycles
2.2 Chip-Select Module
3 S1D13504 Bus Interface
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4 MCF5307 To S1D13504 Interface
4.1 Hardware Connections
Table 4-2: S1D13504 Host Bus Selection
4.3 Memory/Register Mapping
4.4 MCF5307 Chip Select Configuration
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7.2 Motorola MCF5307 Processor
Local Motorola sales office or authorized distributor.
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2 Interfacing to the MC68328
2.1 The 68328 System Bus
2.2 Chip-Select Module
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4 MC68328 To S1D13504 Interface
Figure 4-1: Block Diagram of MC68328 to S1D13504 Interface - MC68000 Bus 1 Interface Mode
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Table 4-2: S1D13504 Host Bus Selection
4.3 MC68328 Chip Select Configuration
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7.2 Motorola MC68328 Processor
Local Motorola sales office or authorized distri butor.
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2 Interfacing to the MPC821
2.1 The MPC8xx System Bus
2.2 MPC821 Bus Overview
2.2.1 Normal (Non-Burst) Bus Transactions
2.1.3 Burst Cycles
2.3 Memory Controller Module
2.3.1 General-Purpose Chip Select Module (GPCM)
2.3.2 User-Programmable Machine (UPM)
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4 MPC821 to S1D13504 Interface
4.2 Hardware Connections
Table 4-1: List of Connections from MPC821ADS to S1D13504 (Continued)
4.3 S1D13504 Hardware Configuration
Table 4-2: Summary of Power-On/Reset Options
Table 4-2: Host Bus Interface Select ion
4.4 Register/Memory Mapping
4.5 MPC821 Chip Select Configuration
4.6 Test Software
4.6.1 Source Code
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7.2 Motorola MPC821 Processor
Local Motorola sales office or authorized distributor.
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2 Interfacing to the PC Card Bus
2.1 The PC Card System Bus
2.1.1 PC Card Overview
2.1.2 Memory Access Cycles
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4 PC Card to S1D13504 Interface
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4.3 PAL Equations
4.4 Register/Memory Mapping
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7.2 PC Card Standard
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List of Tables
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2 Interfacing to the TX3912
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4 Direct Connection to the Toshiba TX3912
Figure 4-1: Typical Implementation of TX3912 to S1D13504 Direct Connection
4.2 Memory Mapping and Aliasing
4.3 S1D13504 Hardware Configuration
5 System Design Using the IT8368E PC Card Buffer
5.1 Hardware DescriptionUsing One IT8368E
Figure 5-1: S1D13504 to TX3912 Connection using One IT8368E
IT8368E
Latch
TX3912
5.2 Hardware DescriptionUsing Two IT8368Es
Figure 5-2: S1D13504 to TX3912 Connection using Two IT8368E
TX3912
5.3 IT8368E Configuration
5.4 Memory Mapping and Aliasing
5.5 S1D13504 Configuration
6 Software
7 References
7.1 Documents
7.2 Document Sources
8 Technical Support
8.1 EPSON LCD/CRT Controllers (S1D13504)
8.2 Toshiba MIPS TX3912 Processor 8.3 ITE IT8368E
