Epson Research and Development

Page 119

Vancouver Design Center

 

 

 

11 Clocking

11.1 Maximum MCLK: PCLK Ratios

Table 11-1: Maximum PCLK Frequency with EDO-DRAM

 

Display type

NRC

 

Maximum PCLK Allowed

 

 

 

 

 

 

 

 

1 bpp

2 bpp

4 bpp

8 bpp

16 bpp

 

 

 

 

 

 

 

 

 

 

 

Single Panel.

 

 

 

 

 

 

CRT.

 

 

 

 

 

 

• Dual Monochrome/Color Panel with Half Frame Buffer

 

 

 

 

 

 

 

Disabled.

5, 4, 3

 

 

MCLK

 

 

• Simultaneous CRT + Single Panel.

 

 

 

 

 

 

Simultaneous CRT + Dual Monochrome/Color Panel

 

 

 

 

 

 

 

with Half Frame Buffer Disabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dual Monochrome Panel with Half Frame Buffer

5

MCLK/2

MCLK/2

MCLK/2

MCLK/2

MCLK/3

 

Enabled.

 

 

 

 

 

 

 

4

MCLK/2

MCLK/2

MCLK/2

MCLK/2

MCLK/3

• Simultaneous CRT + Dual Monochrome Panel with

 

 

 

 

 

 

3

MCLK

MCLK

MCLK/2

MCLK/2

MCLK/2

 

Half Frame Buffer Enable.

 

 

 

 

 

 

 

 

Dual Color Panel with Half Frame Buffer Enabled.

5

MCLK/2

MCLK/2

MCLK/2

MCLK/3

MCLK/3

Simultaneous CRT + Dual Color Panel with Half

 

 

 

 

 

 

4

MCLK/2

MCLK/2

MCLK/2

MCLK/2

MCLK/3

 

Frame Buffer Enable.

 

 

 

 

 

 

 

3

MCLK/2

MCLK/2

MCLK/2

MCLK/2

MCLK/3

 

 

 

 

 

 

 

 

 

 

 

Table 11-2: Maximum PCLK Frequency with FPM-DRAM

 

 

 

 

 

 

 

 

 

 

Display type

NRC

 

Maximum PCLK allowed

 

 

 

 

 

 

 

 

1 bpp

2 bpp

4 bpp

8 bpp

16 bpp

 

 

 

 

 

 

 

 

 

 

 

Single Panel.

 

 

 

 

 

 

CRT.

 

 

 

 

 

 

• Dual Monochrome/Color Panel with Half Frame Buffer

 

 

 

 

 

 

 

Disabled.

5, 4, 3

 

 

MCLK

 

 

Simultaneous CRT + Single Panel.

 

 

 

 

 

 

Simultaneous CRT + Dual Monochrome/Color Panel

 

 

 

 

 

 

 

with Half Frame Buffer Disabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dual Monochrome Panel with Half Frame Buffer

5

MCLK/2

MCLK/2

MCLK/2

MCLK/2

MCLK/3

 

Enabled.

 

 

 

 

 

 

 

4

MCLK/2

MCLK/2

MCLK/2

MCLK/2

MCLK/2

Simultaneous CRT + Dual Monochrome Panel with

 

 

 

 

 

 

3

MCLK

MCLK

MCLK

MCLK/2

MCLK/2

 

Half Frame Buffer Enable.

 

 

 

 

 

 

 

 

Dual Color Panel with Half Frame Buffer Enabled.

5

MCLK/2

MCLK/2

MCLK/2

MCLK/2

MCLK/3

Simultaneous CRT + Dual Color Panel with Half

 

 

 

 

 

 

4

MCLK/2

MCLK/2

MCLK/2

MCLK/2

MCLK/3

 

Frame Buffer Enable.

 

 

 

 

 

 

 

3

MCLK/2

MCLK/2

MCLK/2

MCLK/2

MCLK/2

 

 

 

 

 

 

 

 

 

 

Hardware Functional Specification

S1D13504

Issue Date: 01/01/30

X19A-A-002-18

Page 125
Image 125
Epson S1D13504 manual Clocking, Maximum Mclk Pclk Ratios, Display type, Maximum Pclk Allowed Bpp 16 bpp