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Epson Research and Development

 

Vancouver Design Center

 

 

If UDS and/or LDS are required for their alternate I/O functions, then the 68328 to S1D13504 interface may be realized using the S1D13504 Generic bus interface mode. The electrical connections required for this interface are shown below. Note that in either case, the DTACK signal must be made available for the S1D13504, since it inserts a variable number of wait states depending upon CPU/LCD synchronization and the LCD panel display mode being used. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle.

MC68328

A21

A[20:1]

D[15:0]

CSB3

DTACK

UWE

LWE

OE

CLK0

Vcc

470

System RESET

S1D13504

M/R#

AB[20:1]

SD[15:0]

CS#

WAIT#

WE1#

WE0#

RD1#

RD0#

BUSCLK

RESET#

Note:

When connecting the S1D13504/55 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13504/55 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

Figure 4-2: Block Diagram of MC68328 to S1D13504 Interface - Generic Interface Mode

The S1D13504 requires a 2M byte address space for the display buffer, plus a few more locations to access its internal registers. To accommodate this relatively large block size, it is preferable to use one of the chip selects from groups A or B, but this is not required. Virtually any chip select other than CSA0 or CSD3 would be suitable for the S1D13504 interface.

S1D13504

Interfacing to the Motorola MC68328 "Dragonball" Microprocessor

X19A-G-013-02

Issue Date: 01/02/02

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Image 432
Epson S1D13504 manual CSB3 Dtack UWE LWE CLK0