Epson S1D13504 6.2 Non-ISA B us Support, 6.3 DRAM Support, 6.4 Decode Logic, 6.5 Clock Input Support

Page 14 Epson Research and Development
Vancouver Design Center
S1D13504 S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual
X19A-G-004-06 Issue Date: 01/02/02
6.2 Non-ISA B us Support
This evaluation board is specifically designed to support the standard 16-bit ISA bus, however, the
S1D13504 directly supports many other host bus interfaces. Header strips (H1 and H2) have been
provided and contain all the necessary IO pins to interface to these buses. See Section 4, “CPU / BUS
Interface Connector Pinouts” on page 10; Table 2-1 “Configuration DIP Switch Settings,” on page
8; and Table 2-3 “Jumper Settings,” on page 8 for details.
When using the header strips to provide the bus interface observe the following:
•All IO signals on the ISA bus card edge must be isolated from the ISA bus (do not plug the card
into a computer). Voltage lines are provided on the header strips.
•U3, a TIBPAL22V10 PAL, is currently used to provide the S1D13504 CS# (pin 4), M/R# (pin 5)
and other decode logic signals for ISA bus use. This functionality must now be provided exter-
nally; remove the PAL from its socket to eliminate conflicts resulting from two different outputs
driving the same input. Refer to Table 5-1: “Host Bus Interface Pin Mapping,” on page 12 for
connection details.
Note
When using a 3.3V CPU Interface, JP2 must be used to configure the S1D13504 IO VDD to
3.3V. In this configuration all S1D13504 IO pins are configured for 3.3V output (e.g. LCD inter-
face, DRAM interface, RAMDAC interface, etc.). Although the DRAM and RAMDAC devices
are 5.0V parts, they only require a TTL VIH of 2.4V, therefore they will operate correctly with
the CMOS level output drive of the S1D13504.
6.3 DRAM Support
The S1D13504 supports 256K x 16 as well as 1M x 16 DRAM (FPM and EDO) in symmetrical and
asymmetrical formats.
The S5U13504B00C board supports 5.0V 1M x 16 EDO-DRAM (42-pin SOJ package) in symmet-
rical format, providing a 2M byte display buffer.
6.4 Decode Logic
This board design utilizes the Generic MPU Interface of the S5U13504 (see the S1D13504
Hardware Functional Specification, document number X19A-A-002-xx).
All required decode logic between the ISA bus and the S1D13504 is provided through a
TIBPAL22V10 PAL (U3, socketed).
6.5 Clock Input Support
The input clock frequency can be up to 40.0MHz for the S1D13504. A 40.0MHz oscillator (U4,
socketed) is provided as the clock (CLKI) source.