Epson Research and Development

Page 45

Vancouver Design Center

 

 

 

Table 7-5: Generic MPU Interface Asynchronous Timing

Symbol

Parameter

Min

Max

Units

 

 

 

 

 

TBCLK

Bus clock period

25

 

ns

t1

RD0#, RD1#, WE0#, WE1# low to CS# low

4

 

ns

 

 

 

 

 

t2

A[20:0], M/R# valid to RD0#, RD1#, WE0#, WE1# low

0

 

ns

 

 

 

 

 

t3

RD0#, RD1#, WE0#, WE1# high to A[20:0], CS#, M/R# invalid and CS# high

0

 

ns

 

 

 

 

 

t41

CS# low to WAIT# driven low

1

7

ns

t5

RD0#, RD1#, WE0#, WE1# high to WAIT# high impedance

1

6

ns

 

 

 

 

 

t6

WE0#, WE1# low to D[15:0] valid (write cycle)

 

20

ns

 

 

 

 

 

t7

D[15:0] hold from WE0#, WE1# high (write cycle)

0

 

ns

 

 

 

 

 

t82

RD0#, RD1# low to D[15:0] driven (read cycle)

3

15

ns

t9

D[15:0] valid to WAIT# high (read cycle)

0

 

 

 

 

 

 

 

t10

RD0#, RD1# high to D[15:0] high impedance (read cycle)

2

10

 

 

 

 

 

 

1.If the S1D13504 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later.

2.If the S1D13504 host interface is disabled, the timing for D[15:0] driven is relative to the fall- ing edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0] and M/R# become valid,

whichever occurs later.

Hardware Functional Specification

S1D13504

Issue Date: 01/01/30

X19A-A-002-18

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Image 51
Epson S1D13504 manual T82