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Epson Research and Development

 

Vancouver Design Center

 

 

3 S1D13504 Host Bus Interface

The S1D13504 implements a 16-bit Generic MPU host bus interface which is used to interface to the VR4102 microprocessor. The Generic MPU host bus interface is the least processor-specific interface mode supported by the S1D13504 and was chosen to implement this interface due to the simplicity of its timing.

The Generic MPU host bus interface is selected by the S1D13504 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.

Note

After reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh]) will be set to logic ‘1’, meaning that the S1D13504 will not respond to any host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not work- ing, so it is important to remember to clear this bit before proceeding with debugging.

3.1 Generic MPU Host Bus Interface Pin Mapping

The following table shows the functions of each host bus interface signal.

Table 3-1: Generic MPU Host Bus Interface Pin Mapping

S1D13504

Generic MPU

Pin Names

 

 

 

AB[20:1]

A[20:1]

 

 

AB0

A0

 

 

DB[15:0]

D[15:0]

 

 

WE1#

WE1#

 

 

M/R#

External Decode

 

 

CS#

External Decode

 

 

BUSCLK

BCLK

 

 

BS#

Connect to IO VDD

RD/WR#

RD1#

 

 

RD#

RD0#

 

 

WE0#

WE0#

 

 

WAIT#

WAIT#

 

 

RESET#

RESET#

 

 

S1D13504

Interfacing to the NEC VR4102™ Microprocessor

X19A-G-007-07

Issue Date: 01/02/02

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Epson manual S1D13504 Host Bus Interface