Epson Research and Development

Page 17

Vancouver Design Center

TX3912

 

S1D13504

 

 

A[12:0]

 

AB[12:0]

ENDIAN

 

 

 

 

AB[20:13]

D[31:24]

 

DB[7:0]

D[23:16]

 

DB[15:8]

VDD

System RESET

RESET#

pull-up

 

CARDxWAIT*

 

WAIT#

 

 

DCLKOUT

LHA23

M/R#

 

Clock divider

 

IT8368E

...or...

 

 

 

 

Oscillator

BUSCLK

LHA[20:13],

See text

CLKI

 

 

 

LHA23

 

 

 

+3.3V

IO VDD, CORE VDD

 

 

IT8368E

 

 

LHA23/MFIO10

 

WE1#

LHA22/MFIO9

 

WE0#

 

 

LHA21/MFIO8

 

RD1#

 

 

LHA20/MFIO7

 

RD0#

LHA19/MFIO6

Chip Select

CS#

 

 

 

Logic

 

Notes: The Chip Select Logic shown above is necessary to guarantee the timing parameter t1

of the Generic MPU Host Bus Interface Asynchronous Timing (for details refer to the S1D13504 Hardware Functional Specification, document number X19A-A-002-xx).

When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions that amy reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).

Figure 5-2: S1D13504 to TX3912 Connection using Two IT8368E

Note

For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping”.

Interfacing to the Toshiba MIPS TX3912 Processor

S1D13504

Issue Date: 01/02/02

X19A-G-012-04

Page 497
Image 497
Epson manual S1D13504 to TX3912 Connection using Two IT8368E