Page 60

Epson Research and Development

 

Vancouver Design Center

 

 

for (idx = 0; idx < 8; idx++)

{

for (rgb = 0; rgb < 3; rgb++)

{

*(pRegs + 0x26) = *pLUT; pLUT++;

}

}

/*

** Registers 28-2E: RAMDAC - not used in this example. Programmed very

**

similarly to the LUT but all 256 entries are used.

*/

 

/*

 

** Register 23: Performance Enhancement - display

FIFO

enabled, optimum

**

performance.

 

 

 

*/

 

 

 

 

*(pRegs + 0x23) = 0x10;

/* 0001

0000

*/

/*

 

 

 

 

**Register D: Display Mode - 8 BPP, LCD enable.

*/

*(pRegs + 0x0D) = 0x0D;

/* 0000 1101 */

}

S1D13504

Programming Notes and Examples

X19A-G-002-07

Issue Date: 01/02/01

Page 198
Image 198
Epson S1D13504 manual Fifo