Epson S1D13504 6.15 CPU/Bus Interface Header Strips, 6.16 Schematic Notes

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Vancouver Design Center
S5U13504B00C Rev.1.0 ISA Bus Evaluation Board User Manual S1D13504
Issue Date: 01/02/02 X19A-G-004-06
6.15 CPU/Bus Interface Header Strips
All of the CPU/Bus interface pins of the S1D13504 are connected to the header strips H1 and H2 for
easy interface to a CPU/Bus other than the ISA bus.
Refer to Table 4-1 “CPU/BUS Connector (H1) Pinout,” on page 10 and Table 4-2 “CPU/BUS
Connector (H2) Pinout,” on page 11 for specific settings.
Note
These headers only provide the CPU/Bus interface signals from the S1D13504. When another
host bus interface is selected through [MD3:1] configuration, appropriate external decode logic
MUST be used to access the S1D13504. See the section “Host Bus Interface Pin Mapping” of the
S1D13504 Hardware Functional Specificatio n, document number X19A-A-002-xx.
6.16 Schematic Notes
The following schematics are for reference only and may not reflect actual implementation. Please
request updated information before starting any hardware design.