6 JP6 User Timer/Counter Clock Input Selection | Omega OME-A822PG

2.3.6JP6 : User Timer/Counter Clock Input Selection

Internal 2M Clock (default)

INTCLK

EXTCLK

External

Clock

INTCLK

EXTCLK

The OME-A-822PGL/PGH has 3 independent 16 bit timer/counters. The cascaded counter1 and counter2 are used as a pacer timer. Counter0 can be used as a user programmable timer/counter. The user programmable timer/counter can be set to 2M internal clock or external clock ExtCLK, CN3 pin 37. The block diagram is given in section 2.6. The clock source must be very stable. Using the 2M internal clock is strongly suggested.

The OME-A-822PGL/PGH software driver uses counter0 as a machine independent timer. If users program calls the A-822_Delay()subroutine, counter0 will be programmed as a machine independent timer. More detailed information is provided in section 2.6.

NOTE : if you use A-822_Delay(), the JP6 jumper must be set to internal 2M clock.

OME-A-822PGL/PGH Hardware Manual ---- 14

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Omega OME-A822PG manual 6 JP6 User Timer/Counter Clock Input Selection

Contents

User’sGuide Canada MexicoBenelux Czech Republic OME-A-822PGH/PGL Tables of Contents Introduction Connector Features General Description Specifications Power ConsumptionAnalog Inputs 3 A/D Converter Digital I/O DA ConverterInterrupt Channel Programmable Timer/Counter Direct Memory Access Channel DMA Applications Product Check List Hardware Configuration Board Layout I/O Base Address Setting Default base address is Jumper Settings 1 JP1 D/A Internal Reference Voltage Selection 2 JP2 D/A Int/Ext Ref Voltage Selection 3 JP3 Single-ended/Differential Selection 4 JP4 A/D Trigger Source Selection 5 JP5 Interrupt Level Selection 6 JP6 User Timer/Counter Clock Input Selection 7 JP7 DMA Dack Selection JP8 DMA DRQ Selection DRQ JP7 Dack JP8 DMA I/O Register Address Address Read Write 2 A/D Input Buffer Register 1 8254 CounterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register 4 D/I Input Buffer Register Clear Interrupt Request 6 A/D Gain Control Register GAIN3 GAIN2 GAIN1 GAIN0 OME-A-822PGH Gain Control Code Table 7 A/D Multiplex Control Register 8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register Digital I/O CN2 8254 Timer/Counter Counter A/D Conversion 1 A/D conversion flow Polling, interrupt and DMA 2 A/D Conversion Trigger Modes 3 A/D Transfer Modes Delay the settling time refer to Sec .4.6 and Sec Using software trigger and polling transferRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Signal Shielding Use a single connection to frame ground not A.GND or D.GND Using OME-DB-8225 CJC Output CN1 Digital Input Pin Assignment CN1/CN2/CN3 Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals Daughter Board OME-DB-8225OME-DB-37 OME-DB-16P Calibration Description of Variable Resistors D/A Calibration A/D Calibration Diagnostic Utility Introduction OME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Setup Base address selection screen DMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature