DA Converter, Digital I/O, Interrupt Channel | Omega OME-A822PG

1.3.4DA Converter

zChannels : 2 independent

ztype : 12 bit multiplying , Analog device AD-7541

zLinearity : +/- 1/2 bit

zOutput range : 0 to 5V or 0 to 10V jumper selected , may be used with other AC or DC reference input. Maximum output limit +/- 10V

zOutput drive : +/- 5mA

zsettling time : 0.6 microseconds to 0.01% for full scale step

1.3.5 Digital I/O

z	Output port	: 16 bits, TTL compatible
	Output Low: VOL=05.Vmax @IOL = 8 mA max
	Output High: VOH = 2.7Vmin @IOH = -400∝A max
z	Input port	: 16 bits, TTL compatible
	Input Low: VIL=0.8V max; IIL = -0.4mA max
	Input High: VIH=2.0V min; IIL = 20∝A max

1.3.6Interrupt Channel

zLevel : 3,4,5,6,7,10,11,12,14,15, jumper selectable

zEnable : Via control register

OME-A-822PGL/PGH Hardware Manual ---- 6

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Omega OME-A822PG manual DA Converter, Digital I/O, Interrupt Channel

Contents

User’sGuide Canada MexicoBenelux Czech Republic OME-A-822PGH/PGL Tables of Contents Introduction Connector Features General Description Specifications Power ConsumptionAnalog Inputs 3 A/D Converter Interrupt Channel DA ConverterDigital I/O Programmable Timer/Counter Direct Memory Access Channel DMA Applications Product Check List Hardware Configuration Board Layout I/O Base Address Setting Default base address is Jumper Settings 1 JP1 D/A Internal Reference Voltage Selection 2 JP2 D/A Int/Ext Ref Voltage Selection 3 JP3 Single-ended/Differential Selection 4 JP4 A/D Trigger Source Selection 5 JP5 Interrupt Level Selection 6 JP6 User Timer/Counter Clock Input Selection 7 JP7 DMA Dack Selection JP8 DMA DRQ Selection DRQ JP7 Dack JP8 DMA I/O Register Address Address Read Write Conversion is completed, the Ready bit will clear to zero 1 8254 Counter2 A/D Input Buffer Register 3 D/A Output Latch Register 4 D/I Input Buffer Register Clear Interrupt Request 6 A/D Gain Control Register GAIN3 GAIN2 GAIN1 GAIN0 OME-A-822PGH Gain Control Code Table 7 A/D Multiplex Control Register 8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register Digital I/O CN2 8254 Timer/Counter Counter A/D Conversion 1 A/D conversion flow Polling, interrupt and DMA 2 A/D Conversion Trigger Modes 3 A/D Transfer Modes Refer to Sec Using software trigger and polling transferDelay the settling time refer to Sec .4.6 and Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Signal Shielding Use a single connection to frame ground not A.GND or D.GND Using OME-DB-8225 CJC Output CN2 Digital Output Pin Assignment CN1/CN2/CN3 Pin AssignmentCN1 Digital Input Pin Assignment SINGLE-ENDED Signal Mode Differential Signals Daughter Board OME-DB-8225OME-DB-37 OME-DB-16P Calibration Description of Variable Resistors D/A Calibration A/D Calibration Diagnostic Utility Introduction OME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Setup Base address selection screen DMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature