Timer/Counter | Omega OME-A822PG specs

2.68254 Timer/Counter

The 8254 Programmable timer/counter has 4 registers from Base+0 through Base+3. For detailed programming information about the 8254 , please refer to Intel‘s “Microsystem Components Handbook”.The block diagram is shown below.

VCC

CN3.33

10K

	JP6
CN3.37	Cin
CN3.37
	2M

Gate

Cout

Counter 0

CN3.16

Cin : clock input

Cout : clock output

INTCLK : internal clock

CN3 : connector CN3

PACER CLK

Counter 1

Cin Gate Cout

CN3.35

VCC

10K

4M 2M

INTCLK

Counter 2

Cin Gate Cout

CN3.34

The counter0, counter1 and counter2 are all 16 bit counters. Counter 1 and counter 2 are cascaded as a 32 bit timer. This 32 bit timer is used as a pacer timer. The software driver,

A-822_Delay(), uses counter 0 to implement a machine independent timer for settling time delay (sec. 2.4.6 and sec. 2.4.7). If A-822_Delay() is not used, counter0 can be used as

a general purpose timer/counter.

NOTE : When using A-822_Delay() to implement a machine independent timer, the JP6 jumper must be set to internal 2M clock.

OME-A-822PGL/PGH Hardware Manual ---- 26

Image 28

Omega OME-A822PG manual Timer/Counter

Contents

User’sGuide Canada MexicoBenelux Czech Republic OME-A-822PGH/PGL Tables of Contents Introduction Connector Features General Description Specifications Power ConsumptionAnalog Inputs 3 A/D Converter Digital I/O DA ConverterInterrupt Channel Programmable Timer/Counter Direct Memory Access Channel DMA Applications Product Check List Hardware Configuration Board Layout I/O Base Address Setting Default base address is Jumper Settings 1 JP1 D/A Internal Reference Voltage Selection 2 JP2 D/A Int/Ext Ref Voltage Selection 3 JP3 Single-ended/Differential Selection 4 JP4 A/D Trigger Source Selection 5 JP5 Interrupt Level Selection 6 JP6 User Timer/Counter Clock Input Selection 7 JP7 DMA Dack Selection JP8 DMA DRQ Selection DRQ JP7 Dack JP8 DMA I/O Register Address Address Read Write 2 A/D Input Buffer Register 1 8254 CounterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register 4 D/I Input Buffer Register Clear Interrupt Request 6 A/D Gain Control Register GAIN3 GAIN2 GAIN1 GAIN0 OME-A-822PGH Gain Control Code Table 7 A/D Multiplex Control Register 8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register Digital I/O CN2 8254 Timer/Counter Counter A/D Conversion 1 A/D conversion flow Polling, interrupt and DMA 2 A/D Conversion Trigger Modes 3 A/D Transfer Modes Delay the settling time refer to Sec .4.6 and Sec Using software trigger and polling transferRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Signal Shielding Use a single connection to frame ground not A.GND or D.GND Using OME-DB-8225 CJC Output CN1 Digital Input Pin Assignment CN1/CN2/CN3 Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals Daughter Board OME-DB-8225OME-DB-37 OME-DB-16P Calibration Description of Variable Resistors D/A Calibration A/D Calibration Diagnostic Utility Introduction OME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Setup Base address selection screen DMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature