Texas Instruments warranty TMS320C6727, TMS320C6726, TMS320C6722, EMIF Electrical Data/Timing

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.11.3 EMIF Electrical Data/Timing

Table 4-5through Table 4-8assume testing over recommended operating conditions (see Figure 4-7through Figure 4-13).

Table 4-5. EMIF SDRAM Interface Timing Requirements

NO.			MIN	MAX UNIT
19	tsu(EM_DV-EM_CLKH)	Input setup time, read data valid on D[31:0] before EM_CLK rising	3	ns
20	th(EM_CLKH-EM_DIV)	Input hold time, read data valid on D[31:0] after EM_CLK rising	1.9	ns

Table 4-6. EMIF SDRAM Interface Switching Characteristics

NO.

1 tc(EM_CLK)

2 tw(EM_CLK)

3td(EM_CLKH-EM_CSV)S

4toh(EM_CLKH-EM_CSIV)S

5td(EM_CLKH-EM_WE-DQMV)S

6toh(EM_CLKH-EM_WE-DQMIV)S

7td(EM_CLKH-EM_AV)S

8toh(EM_CLKH-EM_AIV)S

9td(EM_CLKH-EM_DV)S

10toh(EM_CLKH-EM_DIV)S

11td(EM_CLKH-EM_RASV)S

12toh(EM_CLKH-EM_RASIV)S

13td(EM_CLKH-EM_CASV)S

14toh(EM_CLKH-EM_CASIV)S

15td(EM_CLKH-EM_WEV)S

16toh(EM_CLKH-EM_WEIV)S

17tdis(EM_CLKH-EM_DHZ)S

18tena(EM_CLKH-EM_DLZ)S

PARAMETER	MIN	MAX	UNIT
Cycle time, EMIF clock EM_CLK	10		ns
Pulse width, EMIF clock EM_CLK high or low	3		ns
Delay time, EM_CLK rising to EM_CS[0] valid		7.7	ns
Output hold time, EM_CLK rising to EM_CS[0] invalid	1.15		ns
Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid		7.7	ns
Output hold time, EM_CLK rising to EM_WE_DQM[3:0] invalid	1.15		ns
Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid		7.7	ns
Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0]	1.15		ns
invalid
Delay time, EM_CLK rising to EM_D[31:0] valid		7.7	ns
Output hold time, EM_CLK rising to EM_D[31:0] invalid	1.15		ns
Delay time, EM_CLK rising to EM_RAS valid		7.7	ns
Output hold time, EM_CLK rising to EM_RAS invalid	1.15		ns
Delay time, EM_CLK rising to EM_CAS valid		7.7	ns
Output hold time, EM_CLK rising to EM_CAS invalid	1.15		ns
Delay time, EM_CLK rising to EM_WE valid		7.7	ns
Output hold time, EM_CLK rising to EM_WE invalid	1.15		ns
Delay time, EM_CLK rising to EM_D[31:0] 3-stated		7.7	ns
Output hold time, EM_CLK rising to EM_D[31:0] driving	1.15		ns

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