Texas Instruments TMS320C6727, TMS320C6726, TMS320C6722, Phase-LockedLoop PLL, 43.PLL Topology

TMS320C6727, TMS320C6726, TMS320C6722

Floating-Point Digital Signal Processors

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SPRS268E –MAY 2005 –REVISED JANUARY 2007

4.18 Phase-Locked Loop (PLL)

4.18.1 PLL Device-Specific Information

The C672x DSP generates the high-frequency internal clocks it requires through an on-chip PLL.

The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the CLKIN pin. The PLL outputs four clocks that have programmable divider options. Figure 4-43illustrates the PLL Topology.

The PLL is disabled by default after a device reset. It must be configured by software according to the allowable operating conditions listed in Table 4-40before enabling the DSP to run from the PLL by setting PLLEN = 1.

Clock

Input from CLKIN or

OSCIN

				PLLEN
				(PLL_CSR[0])
Divider	PLLREF	PLL	PLLOUT
D0			1	Divider	SYSCLK1
		x4 to x25
(/1 to /32)
				D1
			0	(/1 to /32)
				Divider	SYSCLK2
				D2
				(/1 to /32)
				Divider	SYSCLK3
				D3
				(/1 to /32)
					AUXCLK

CPU and Memory

Peripherals and dMAX

EMIF

McASP0,1,2

Figure 4-43. PLL Topology

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