POST Code | Function | Phase | Component |
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0x32 | Program the Egress port timings | PEI | chipset/MRC |
0x33 | Program the Memory IO registers | PEI | chipset/MRC |
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0x34 | Perform steps required before JEDEC | PEI | chipset/MRC |
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|
0x35 | Perform JEDEC memory initialization for all memory | PEI | chipset/MRC |
| rows |
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0x36 | Setup DRAM control register for normal operation | PEI | chipset/MRC |
| and enable |
|
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0x37 | Do ZQ calibration for DDR3 | PEI | chipset/MRC |
|
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0x38 | Perform final Dra/Drb programming, Set the mode of | PEI | chipset/MRC |
| operation for the memory channels |
|
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|
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0x39 | Set Enhanced addressing mode for each channel | PEI | chipset/MRC |
|
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|
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0x40 | Perform steps required after JEDEC init | PEI | chipset/MRC |
|
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|
|
0x41 | Program the receive enable reference timing control | PEI | chipset/MRC |
| register |
|
|
|
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|
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0x42 | Post receive enable initialization | PEI | chipset/MRC |
|
|
|
|
0x43 | Enable sense amps. Reset read/write DQS pointers | PEI | chipset/MRC |
|
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|
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0x44 | Perform ME steps | PEI | chipset/MRC |
|
|
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0x45 | Clear DRAM initialization bit in the ICH. | PEI | chipset/MRC |
|
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|
0x46 | Program Thermal Management | PEI | chipset/MRC |
|
|
|
|
0x47 | Program TS on DIMM | PEI | chipset/MRC |
|
|
|
|
0x48 | Program TS on Board | PEI | chipset/MRC |
|
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|
|
0xAF | Exit MRC | PEI | chipset/MRC |
|
|
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|
0xE0 | #define MEM_ERR_BAD_DIMM (S11) | PEI | chipset/MRC |
|
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|
|
0xE1 | #define MEM_ERR_ECC_DIMM (S06) | PEI | chipset/MRC |
|
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|
0xE2 | #define MEM_ERR_SIDES (S07) | PEI | chipset/MRC |
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0xE3 | #define MEM_ERR_WIDTH (S08, S10) | PEI | chipset/MRC |
|
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|
|
0xE4 | #define MEM_ERR_TRFC (FindTrasTrpTrcd) | PEI | chipset/MRC |
|
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|
|
0xE5 | #define MEM_ERR_CAS_LATENCY (S12, S13) | PEI | chipset/MRC |
|
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|
|
0xE6 | #define MEM_ERR_REFRESH (ProgDrt) | PEI | chipset/MRC |
|
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|
|
0xE7 | #define MEM_ERR_BL8 (S14) | PEI | chipset/MRC |
|
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|
|
0xE9 | #define MEM_ERR_FREQUENCY (findTCLTacTClk, | PEI | chipset/MRC |
| S13, S12, ProgramGraphicsFrequency, |
|
|
| ProgMchOdt, GetPlatformData) |
|
|
|
|
|
|
0xEA | #define MEM_ERR_SIZE (S14) | PEI | chipset/MRC |
|
|
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|
0xEC | #define MEM_ERR_TRAS (FindTrasTrpTrcd) | PEI | chipset/MRC |
|
|
|
|
0xED | #define MEM_ERR_TRP (FindTrasTrpTrcd) | PEI | chipset/MRC |
|
|
|
|
0xEE | #define MEM_ERR_TRCD (FindTrasTrpTrcd) | PEI | chipset/MRC |
|
|
|
|
0xEF | #define MEM_ERR_TWR (FindTrasTrpTrcd) | PEI | chipset/MRC |
|
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|
0xF0 | #define MEM_ERR_RCVEN_FINDLOW | PEI | chipset/MRC |
| (CalibrateRcvenForGroup) |
|
|
|
|
|
|
0xF1 | #define MEM_ERR_RCVEN_FINDEDGE | PEI | chipset/MRC |
| (CalibrateRcvenForGroup) |
|
|
|
|
|
|
0xF2 | #define MEM_ERR_RCVEN_FINDPREAMBLE | PEI | chipset/MRC |
| (CalibrateRcvenForGroup) |
|
|
|
|
|
|
0xF6 | #define MEM_ERR_RCVEN_PREAMBLEEDGE | PEI | chipset/MRC |
| (CalibrateRcvenForGroup) |
|
|
|
|
|
|
146 | Chapter 4 |
