4.4.2Chipset

Phoenix-Award BIOS CMOS Setup Utility

Advanced

Chipset

 

Select Menu

 

 

 

DRAM Configuration

 

Item Specific Help

Upstream LDT Bus Width

[16 bit]

 

Downstream LDT Bus Width

[16 bit]

DRAM timing and

LDT Bus Frequency

[Auto]

control

VLink Mode Selection

[By Auto]

 

PEG Data Scrambling

[Auto]

 

PE0-PE3 Data Scrambling

[Enable]

 

Init Display First

[PCI Slot

 

Chipset Vcore Adjustment

[+1.6 V]

 

 

 

 

F1:Help

↑↓

: Select Item

-/+:

Change

Value

F5: Setup Defaults

ESC: Exit

→←

: Select Menu

Enter:

Select

Sub-menu

F10: Save and Exit

 

 

 

 

 

 

 

DRAM Configuration

The items in this sub-menu show the DRAM-related information auto-detected by the BIOS.

Phoenix-Award BIOS CMOS Setup Utility

Advanced

 

DRAM Configuration

Select Menu

 

 

 

 

 

Current DRAM Frequency

 

166 MHz

Item Specific Help

Max Memclock (MHz)

 

[

Auto

]

 

CAS# latency (Tcl)

 

[Auto]

Place an artificial

RAS# to CAS# delay

(Trcd)

[Auto]

memory clock limit on

Min RAS# active time(Tras)

[Auto]

the system. Memory is

Row precharge Time

(Trp)

[Auto]

prevented from

Master ECC Enable

 

[Enabled]

 

 

 

 

 

running faster than

 

 

 

 

 

this frequency.

 

 

 

 

 

 

F1:Help

↑↓

: Select Item

-/+:

Change

Value

F5: Setup Defaults

ESC: Exit

→←

: Select Menu

Enter:

Select

Sub-menu

F10: Save and Exit

 

 

 

 

 

 

 

Current DRAM Frequency

Shows the Transfer mode. This item is not configurable.

Max Memclock (MHz) [Auto]

Sets the maximum operating memory clock.

Configuration options: [Auto] [DDR200] [DDR266] [DDR333] [DDR400]

ASUS A8V-E Deluxe

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