2.4.3Memory mirroring and sparing technology
The Intel® 5400 chipset supports the memory mirroring and sparing technology. Refer to the below sections:
Memory Mirroring:
When enabling memory mirroring function in the BIOS setting (please refer the section 4.4.2 Chipset Configuration and configure the option Memory Branch Mode as Branch Mirroring), Branch 1 contains a replicate copy of the data
in Branch 0. The DIMMs must cover the same slot position on both branches. DIMMs that cover a slot position must be identical with respect to size, speed, and organization. DIMMs within a slot position must match each other, but aren’t required to match adjacent slot positions.
And the total memories size will be the half of all installed memories.
The below two memory configurations were required to operate in mirrored mode.
1.Configuration 1 (Mirroring): Four memories population
MCH
0) 0:Channel (Slot 00 DIMM |
| 0) 1:Channel (Slot 01 DIMM |
| 1) 0:Channel (Slot 10 DIMM |
| 1) 1:Channel (Slot 11 DIMM |
| 2) 0:Channel (Slot 20 DIMM |
| 2) 1:Channel (Slot 21 DIMM |
| 3) 0:Channel (Slot 30 DIMM |
| 3) 1:Channel (Slot 31 DIMM |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Branch 0 | Branch 1 (Mirror) |
2.Configuration 2 (Mirroring) : Eight memories population
MCH
0) 0:Channel (Slot 00 DIMM |
| 0) 1:Channel (Slot 01 DIMM |
| 1) 0:Channel (Slot 10 DIMM |
| 1) 1:Channel (Slot 11 DIMM |
| 2) 0:Channel (Slot 20 DIMM |
| 2) 1:Channel (Slot 21 DIMM |
| 3) 0:Channel (Slot 30 DIMM |
| 3) 1:Channel (Slot 31 DIMM |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Branch 0 | Branch 1 (Mirror) |
Chapter 2: Hardware information |