Atmel AT89C5132 6.3 AC Characteristics

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4173ES–USB–09/07
AT89C5132
6.3 AC Characteristics
6.3.1 External 8-bit Bus Cycles
6.3.1.1 Definition of Symbols
Table 6. External 8-bit Bus Cycles Timing Symbol Definitions
6.3.1.2 Timings
Test conditions: capacitive load on all pins = 50 pF.
Table 7. External 8-bit Bus Cycle – Data Read AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Signals Conditions
A Address H High
D Data In L Low
L ALE V Valid
Q Data Out X No Longer Valid
RRD ZFloating
WWR
Symbol Parameter
Variable Clock
Standard Mode Variab le Cloc k X2 Mode
UnitMin Max Min Max
TCLCL Clock Period 50 50 ns
TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns
TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLAX Address hold after ALE Low TCLCL-20 0 .5·TCLCL-20 ns
TLLRL ALE Low to RD Low 3·TCLCL-30 1.5·TCLCL-30 ns
TRLRH RD Pulse Width 6·TCLCL-25 3·TCLCL-25 ns
TRHLH RD high to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns
TAVDV Address Valid to Valid Data In 9·TCLCL-65 4.5·TCLCL-65 ns
TAVRL Address Valid to RD Low 4·TCLCL-30 2·TCLCL-30 ns
TRLDV RD Low to Valid Data 5·TCLCL-30 2.5·TCLCL-30 ns
TRLAZ RD Low to Address Float 0 0 ns
TRHDX Data Hold After RD High 0 0 ns
TRHDZ Instruction Float After RD High 2·TCLCL-25 TCLCL-25 ns