33
4173ES–USB–09/07
AT89C5132
6.3.9.2 Timings Table 22. Externa l Clock AC TimingsVDD = 2.7 to 3.3V, TA= -40 to +85°C6.3.9.3 WaveformsFigure 6-23. External Clock WaveformFigure 6-24. AC Testing Input/Output Waveforms

Notes: 1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0.

2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.

Figure 6-25. Float Waveforms

Note: For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a

100 mV change from the loading VOH/VOL level occurs with IOL/IOH = ±20 mA.

Symbol Parameter Min Max Unit
TCLCL Clock Period 50 ns
TCHCX High Time 10 ns
TCLCX Low Time 10 ns
TCLCH Rise Time 3 ns
TCHCL Fall Time 3 ns
TCR Cyclic Ratio in X2 Mode 40 60 %
0.45 V
TCLCL
VDD - 0.5 VIH1
VIL
TCHCX
TCLCH
TCHCL
TCLCX
0.45 V
V
DD - 0.5 0.7 VDD
0.3 VDD
VIH min
VIL max
INPUTS OUTPUTS
VLOAD
VOH - 0.1V
VOL + 0.1V
VLOAD + 0.1V
VLOAD - 0.1V Timing Reference Points