Atmel AT89C5132 22, Table 11. External IDE 16-bit Bus Cycle Data Write AC Timings

22
4173ES–USB–09/07
AT89C5132
Table 10. Externa l IDE 16-bit Bus Cycle – Data Read AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Table 11. External IDE 16-bit Bus Cycle – Data Write AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Symbol Parameter
Variable Clock
Standard Mode Variable Clock X2 Mode
UnitMin Max Min Max
TCLCL Clock Period 50 50 ns
TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns
TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLRL ALE Low to RD Low 3·TCLCL-30 1.5·TCLCL-30 ns
TRLRH RD Pulse Width 6·TCLCL-25 3·TCLCL-25 ns
TRHLH RD high to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns
TAVDV Address Valid to Valid Data In 9·TCLCL-65 4.5·TCLCL-65 ns
TAVRL Address Valid to RD Low 4·TCLCL-30 2·TCLCL-30 ns
TRLDV RD Low to Valid Data 5·TCLCL-30 2.5·TCLCL-30 ns
TRLAZ RD Low to Address Float 0 0 ns
TRHDX Data Hold After RD High 0 0 ns
TRHDZ Instruction Float After RD High 2·TCLCL-25 TCLCL-25 ns
Symbol Parameter
Variable Clock
Standard Mode Variable C lock X2 Mode
UnitMin Max Min Max
TCLCL Clock Period 50 50 ns
TLHLL ALE Pulse Width 2·TCLCL-15 TCLCL-15 ns
TAVLL Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns
TLLWL ALE Low to WR Low 3·TCLCL-30 1.5·TCLCL-30 ns
TWLWH WR Pulse Width 6·TCLCL-25 3·TCLCL-25 ns
TWHLH WR High to ALE High TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns
TAVWL Address Valid to WR Low 4·TCLCL-30 2·TCLCL-30 ns
TQVWH Data Valid to WR High 7·TCLCL-20 3.5·TCLCL-20 ns
TWHQX Data Hold after WR High TCLCL-15 0.5·TCLCL-15 ns